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Commit 19d4df3e authored by Ping Li's avatar Ping Li
Browse files

drm/msm/sde: Add LTM VLUT feature support via LUT_DMA 



Add LTM VLUT feature support using LUT DMA framework.

Change-Id: Ieac3dafed650d21f10741f12c746d3dfbf7b5029
Signed-off-by: default avatarPing Li <pingli@codeaurora.org>
parent 51f73581

drivers/gpu/drm/msm/sde/sde_color_processing.c

+44 −0
Original line number Diff line number Diff line
@@ -505,6 +505,47 @@ static int set_lm_gc_feature(struct sde_hw_dspp *hw_dspp, 
	return ret;

}



static int set_ltm_init_feature(struct sde_hw_dspp *hw_dspp,

				   struct sde_hw_cp_cfg *hw_cfg,

				   struct sde_crtc *hw_crtc)

{

	int ret = 0;



	if (!hw_dspp || !hw_dspp->ops.setup_ltm_init)

		ret = -EINVAL;

	else

		hw_dspp->ops.setup_ltm_init(hw_dspp, hw_cfg);



	return ret;

}



static int set_ltm_roi_feature(struct sde_hw_dspp *hw_dspp,

				   struct sde_hw_cp_cfg *hw_cfg,

				   struct sde_crtc *hw_crtc)

{

	int ret = 0;



	if (!hw_dspp || !hw_dspp->ops.setup_ltm_roi)

		ret = -EINVAL;

	else

		hw_dspp->ops.setup_ltm_roi(hw_dspp, hw_cfg);



	return ret;

}



static int set_ltm_vlut_feature(struct sde_hw_dspp *hw_dspp,

				   struct sde_hw_cp_cfg *hw_cfg,

				   struct sde_crtc *hw_crtc)

{

	int ret = 0;



	if (!hw_dspp || !hw_dspp->ops.setup_ltm_vlut)

		ret = -EINVAL;

	else

		hw_dspp->ops.setup_ltm_vlut(hw_dspp, hw_cfg);



	return ret;

}



set_feature_wrapper crtc_feature_wrappers[SDE_CP_CRTC_MAX_FEATURES];
@@ -539,6 +580,9 @@ do { \ 
	wrappers[SDE_CP_CRTC_DSPP_AD_STRENGTH] = set_dspp_ad_strength_feature; \

	wrappers[SDE_CP_CRTC_DSPP_AD_ROI] = set_dspp_ad_roi_feature; \

	wrappers[SDE_CP_CRTC_LM_GC] = set_lm_gc_feature; \

	wrappers[SDE_CP_CRTC_DSPP_LTM_INIT] = set_ltm_init_feature; \

	wrappers[SDE_CP_CRTC_DSPP_LTM_ROI] = set_ltm_roi_feature; \

	wrappers[SDE_CP_CRTC_DSPP_LTM_VLUT] = set_ltm_vlut_feature; \

} while (0)



#define INIT_PROP_ATTACH(p, crtc, prop, node, feature, val) \

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+14 −0
Original line number Diff line number Diff line
@@ -273,6 +273,20 @@ enum { 
	SDE_DSPP_MAX

};



/**

 * LTM sub-features

 * @SDE_LTM_INIT             LTM INIT feature

 * @SDE_LTM_ROI              LTM ROI feature

 * @SDE_LTM_VLUT             LTM VLUT feature

 * @SDE_LTM_MAX              maximum value

 */

enum {

	SDE_LTM_INIT = 0x1,

	SDE_LTM_ROI,

	SDE_LTM_VLUT,

	SDE_LTM_MAX

};



/**

 * PINGPONG sub-blocks

 * @SDE_PINGPONG_TE         Tear check block

drivers/gpu/drm/msm/sde/sde_hw_color_proc_common_v4.h

+41 −0
Original line number Diff line number Diff line
@@ -5,6 +5,8 @@ 
#ifndef _SDE_HW_COLOR_PROC_COMMON_V4_H_

#define _SDE_HW_COLOR_PROC_COMMON_V4_H_



#include "sde_hw_mdss.h"



#define GAMUT_TABLE_SEL_OFF 0x4

#define GAMUT_UPPER_COLOR_OFF 0x8

#define GAMUT_LOWER_COLOR_OFF 0xc
@@ -119,4 +121,43 @@ enum { 
#define SSPP 0

#define DSPP 1



struct sde_ltm_phase_info {

	u32 init_h[LTM_MAX];

	u32 init_v;

	u32 inc_h;

	u32 inc_v;

	bool portrait_en;

	bool merge_en;

};



static inline void sde_ltm_get_phase_info(struct sde_hw_cp_cfg *hw_cfg,

		struct sde_ltm_phase_info *info)

{

	u32 count_v, count_h, num_mixers;



	if (hw_cfg->displayh < hw_cfg->displayv) {

		count_h = 4;

		count_v = 8;

		info->portrait_en = true;

	} else {

		count_h = 8;

		count_v = 4;

		info->portrait_en = false;

	}



	num_mixers = hw_cfg->num_of_mixers;

	if (num_mixers == 1)

		info->merge_en = false;

	else

		info->merge_en = true;



	info->init_h[LTM_0] = (1 << 23);

	info->init_v = (1 << 23);

	info->inc_h = ((count_h - 1) << 24) / (hw_cfg->displayh - 1);

	info->inc_v = ((count_v - 1) << 24) / (hw_cfg->displayv - 1);

	if (info->merge_en)

		info->init_h[LTM_1] = info->init_h[LTM_0] +

			info->inc_h * (hw_cfg->displayh / 2);

}



#endif /* _SDE_HW_COLOR_PROC_COMMON_V4_H_ */

drivers/gpu/drm/msm/sde/sde_hw_dspp.c

+25 −0
Original line number Diff line number Diff line
@@ -196,6 +196,29 @@ static void dspp_ad(struct sde_hw_dspp *c) 
	}

}



static void dspp_ltm(struct sde_hw_dspp *c)

{

	int ret = 0;



	if (c->cap->sblk->ltm.version == SDE_COLOR_PROCESS_VER(0x1, 0x0)) {

		ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_INIT, c->idx);

		if (!ret)

			ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_ROI, c->idx);

		if (!ret)

			ret = reg_dmav1_init_ltm_op_v6(SDE_LTM_VLUT, c->idx);



		if (!ret) {

			c->ops.setup_ltm_init = reg_dmav1_setup_ltm_initv1;

			c->ops.setup_ltm_roi = reg_dmav1_setup_ltm_roiv1;

			c->ops.setup_ltm_vlut = reg_dmav1_setup_ltm_vlutv1;

		} else {

			c->ops.setup_ltm_init = NULL;

			c->ops.setup_ltm_roi = NULL;

			c->ops.setup_ltm_vlut = NULL;

		}

	}

}



static void (*dspp_blocks[SDE_DSPP_MAX])(struct sde_hw_dspp *c);



static void _init_dspp_ops(void)
@@ -211,6 +234,7 @@ static void _init_dspp_ops(void) 
	dspp_blocks[SDE_DSPP_HIST] = dspp_hist;

	dspp_blocks[SDE_DSPP_VLUT] = dspp_vlut;

	dspp_blocks[SDE_DSPP_AD] = dspp_ad;

	dspp_blocks[SDE_DSPP_LTM] = dspp_ltm;

}



static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features)
@@ -288,6 +312,7 @@ void sde_hw_dspp_destroy(struct sde_hw_dspp *dspp) 
{

	if (dspp) {

		reg_dmav1_deinit_dspp_ops(dspp->idx);

		reg_dmav1_deinit_ltm_ops(dspp->idx);

		sde_hw_blk_destroy(&dspp->base);

	}

	kfree(dspp);

drivers/gpu/drm/msm/sde/sde_hw_dspp.h

+20 −0
Original line number Diff line number Diff line
@@ -158,6 +158,26 @@ struct sde_hw_dspp_ops { 
	void (*ad_read_intr_resp)(struct sde_hw_dspp *ctx, u32 event,

			u32 *resp_in, u32 *resp_out);



	/**

	 * setup_ltm_init - setup LTM INIT

	 * @ctx: Pointer to dspp context

	 * @cfg: Pointer to configuration

	 */

	void (*setup_ltm_init)(struct sde_hw_dspp *ctx, void *cfg);



	/**

	 * setup_ltm_roi - setup LTM ROI

	 * @ctx: Pointer to dspp context

	 * @cfg: Pointer to configuration

	 */

	void (*setup_ltm_roi)(struct sde_hw_dspp *ctx, void *cfg);



	/**

	 * setup_ltm_vlut - setup LTM VLUT

	 * @ctx: Pointer to dspp context

	 * @cfg: Pointer to configuration

	 */

	void (*setup_ltm_vlut)(struct sde_hw_dspp *ctx, void *cfg);

};



/**