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Commit 19ce01cc authored by Kishon Vijay Abraham I's avatar Kishon Vijay Abraham I Committed by Bjorn Helgaas
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PCI: dwc: all: Rename cfg_read/cfg_write to read/write 



No functional change. dw_pcie_cfg_read()/dw_pcie_cfg_write() doesn't do
anything specific to access configuration space. It can be just renamed to
dw_pcie_read()/dw_pcie_write() and used to read/write data to dbi space.

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-By: default avatarJoao Pinto <jpinto@synopsys.com>
CC: Jingoo Han <jingoohan1@gmail.com>
CC: Murali Karicheri <m-karicheri2@ti.com>
CC: Stanimir Varbanov <svarbanov@mm-sol.com>
CC: Pratyush Anand <pratyush.anand@gmail.com>
parent 9bcf0a6f

drivers/pci/dwc/pci-dra7xx.c

+8 −8
Original line number Diff line number Diff line
@@ -109,21 +109,21 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx) 
	}



	if (dra7xx->link_gen == 1) {

		dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,

		dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,

			     4, &reg);

		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {

			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);

			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;

			dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +

			dw_pcie_write(pp->dbi_base + exp_cap_off +

				      PCI_EXP_LNKCAP, 4, reg);

		}



		dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,

		dw_pcie_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,

			     2, &reg);

		if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {

			reg &= ~((u32)PCI_EXP_LNKCAP_SLS);

			reg |= PCI_EXP_LNKCAP_SLS_2_5GB;

			dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +

			dw_pcie_write(pp->dbi_base + exp_cap_off +

				      PCI_EXP_LNKCTL2, 2, reg);

		}

	}

drivers/pci/dwc/pci-exynos.c

+2 −2
Original line number Diff line number Diff line
@@ -429,7 +429,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 
	int ret;



	exynos_pcie_sideband_dbi_r_mode(exynos_pcie, true);

	ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val);

	ret = dw_pcie_read(pp->dbi_base + where, size, val);

	exynos_pcie_sideband_dbi_r_mode(exynos_pcie, false);

	return ret;

}
@@ -441,7 +441,7 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 
	int ret;



	exynos_pcie_sideband_dbi_w_mode(exynos_pcie, true);

	ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val);

	ret = dw_pcie_write(pp->dbi_base + where, size, val);

	exynos_pcie_sideband_dbi_w_mode(exynos_pcie, false);

	return ret;

}

drivers/pci/dwc/pci-keystone-dw.c

+2 −2
Original line number Diff line number Diff line
@@ -444,7 +444,7 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 


	addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);



	return dw_pcie_cfg_read(addr + where, size, val);

	return dw_pcie_read(addr + where, size, val);

}



int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
@@ -456,7 +456,7 @@ int ks_dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 


	addr = ks_pcie_cfg_setup(ks_pcie, bus_num, devfn);



	return dw_pcie_cfg_write(addr + where, size, val);

	return dw_pcie_write(addr + where, size, val);

}



/**

drivers/pci/dwc/pcie-designware.c

+6 −6
Original line number Diff line number Diff line
@@ -33,7 +33,7 @@ 


static struct pci_ops dw_pcie_ops;



int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)

int dw_pcie_read(void __iomem *addr, int size, u32 *val)

{

	if ((uintptr_t)addr & (size - 1)) {

		*val = 0;
@@ -54,7 +54,7 @@ int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) 
	return PCIBIOS_SUCCESSFUL;

}



int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)

int dw_pcie_write(void __iomem *addr, int size, u32 val)

{

	if ((uintptr_t)addr & (size - 1))

		return PCIBIOS_BAD_REGISTER_NUMBER;
@@ -108,7 +108,7 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, 
	if (pp->ops->rd_own_conf)

		return pp->ops->rd_own_conf(pp, where, size, val);



	return dw_pcie_cfg_read(pp->dbi_base + where, size, val);

	return dw_pcie_read(pp->dbi_base + where, size, val);

}



static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
@@ -117,7 +117,7 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, 
	if (pp->ops->wr_own_conf)

		return pp->ops->wr_own_conf(pp, where, size, val);



	return dw_pcie_cfg_write(pp->dbi_base + where, size, val);

	return dw_pcie_write(pp->dbi_base + where, size, val);

}



static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
@@ -635,7 +635,7 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, 
	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,

				  type, cpu_addr,

				  busdev, cfg_size);

	ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);

	ret = dw_pcie_read(va_cfg_base + where, size, val);

	if (pp->num_viewport <= 2)

		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,

					  PCIE_ATU_TYPE_IO, pp->io_base,
@@ -673,7 +673,7 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, 
	dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,

				  type, cpu_addr,

				  busdev, cfg_size);

	ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);

	ret = dw_pcie_write(va_cfg_base + where, size, val);

	if (pp->num_viewport <= 2)

		dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,

					  PCIE_ATU_TYPE_IO, pp->io_base,

drivers/pci/dwc/pcie-designware.h

+2 −2
Original line number Diff line number Diff line
@@ -145,8 +145,8 @@ struct pcie_host_ops { 


u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg);

void dw_pcie_writel_rc(struct pcie_port *pp, u32 reg, u32 val);

int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val);

int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val);

int dw_pcie_read(void __iomem *addr, int size, u32 *val);

int dw_pcie_write(void __iomem *addr, int size, u32 val);

irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);

void dw_pcie_msi_init(struct pcie_port *pp);

int dw_pcie_wait_for_link(struct pcie_port *pp);