Merge "clk: qcom: lagoon: Update CAL_L values for Fabia PLLs" (19b49918) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/clk/qcom/camcc-lagoon.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -179,6 +179,7 @@ static struct pll_vco fabia_vco[] = {
		/* 600MHz configuration */
		static const struct alpha_pll_config cam_cc_pll0_config = {
		.l = 0x1F,
		.cal_l = 0x22,
		.alpha = 0x4000,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002067,
		@@ -234,6 +235,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
		/* 808MHz configuration */
		static const struct alpha_pll_config cam_cc_pll1_config = {
		.l = 0x2A,
		.cal_l = 0x2C,
		.alpha = 0x1555,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002067,
		@@ -357,6 +359,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = {
		/* 384MHz configuration */
		static const struct alpha_pll_config cam_cc_pll3_config = {
		.l = 0x14,
		.cal_l = 0x16,
		.alpha = 0x0,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002067,

drivers/clk/qcom/dispcc-lagoon.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -120,7 +120,7 @@ static struct pll_vco fabia_vco[] = {

		static const struct alpha_pll_config disp_cc_pll0_config = {
		.l = 0x3A,
		.cal_l = 0x3F,
		.cal_l = 0x31,
		.alpha = 0x5555,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002067,

drivers/clk/qcom/gpucc-lagoon.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -135,7 +135,7 @@ static struct clk_fixed_factor crc_div = {
		/* 514MHz Configuration*/
		static const struct alpha_pll_config gpu_cc_pll1_config = {
		.l = 0x1A,
		.cal_l = 0x3F,
		.cal_l = 0x3D,
		.alpha = 0xC555,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002067,

drivers/clk/qcom/npucc-lagoon.c

+10 −7

Original line number	Diff line number	Diff line
		@@ -110,6 +110,7 @@ static struct pll_vco fabia_vco[] = {
		/* 537.60MHz Configuration */
		static struct alpha_pll_config npu_cc_pll0_config = {
		.l = 0x1C,
		.cal_l = 0x3F,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002067,
		.test_ctl_val = 0x40000000,
		@@ -147,6 +148,7 @@ static struct clk_alpha_pll npu_cc_pll0 = {
		/* 300MHz Configuration */
		static struct alpha_pll_config npu_cc_pll1_config = {
		.l = 0xF,
		.cal_l = 0x33,
		.alpha = 0xA000,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002067,
		@@ -182,6 +184,7 @@ static struct clk_alpha_pll npu_cc_pll1 = {
		/* 250MHz Configuration */
		static struct alpha_pll_config npu_q6ss_pll_config = {
		.l = 0xD,
		.cal_l = 0x1E,
		.alpha = 0x555,
		.config_ctl_val = 0x20485699,
		.config_ctl_hi_val = 0x00002067,
		@@ -228,11 +231,11 @@ static struct clk_fixed_factor npu_cc_crc_div = {

		static const struct freq_tbl ftbl_npu_cc_cal_hm0_clk_src[] = {
		F(100000000, P_NPU_CC_CRC_DIV, 1, 0, 0),
		F(192000000, P_NPU_CC_CRC_DIV, 1, 0, 0),
		F(268800000, P_NPU_CC_CRC_DIV, 1, 0, 0),
		F(403200000, P_NPU_CC_CRC_DIV, 1, 0, 0),
		F(515000000, P_NPU_CC_CRC_DIV, 1, 0, 0),
		F(650000000, P_NPU_CC_CRC_DIV, 1, 0, 0),
		F(850000000, P_NPU_CC_CRC_DIV, 1, 0, 0),
		F(748800000, P_NPU_CC_CRC_DIV, 1, 0, 0),
		{ }
		};

		@@ -253,11 +256,11 @@ static struct clk_rcg2 npu_cc_cal_hm0_clk_src = {
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_MIN] = 100000000,
		[VDD_LOWER] = 268800000,
		[VDD_LOW] = 403200000,
		[VDD_LOW_L1] = 515000000,
		[VDD_NOMINAL] = 650000000,
		[VDD_HIGH] = 850000000},
		[VDD_LOWER] = 192000000,
		[VDD_LOW] = 268800000,
		[VDD_LOW_L1] = 403200000,
		[VDD_NOMINAL] = 515000000,
		[VDD_HIGH] = 748800000},
		},
		};