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Commit 193c9d23 authored by Paul Walmsley's avatar Paul Walmsley Committed by Rob Herring
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Documentation: DT bindings: add more Tegra chip compatible strings 

Align compatible strings for several IP blocks present on Tegra chips
with the latest doctrine from the DT maintainers:

http://marc.info/?l=devicetree&m=142255654213019&w=2

The primary objective here is to avoid checkpatch warnings, per:

http://marc.info/?l=linux-tegra&m=142201349727836&w=2



DT binding text files have been updated for the following IP blocks:

- PCIe
- SOR
- SoC timers
- AHB "gizmo"
- APB_MISC
- pinmux control
- UART
- PWM
- I2C
- SPI
- RTC
- PMC
- eFuse
- AHCI
- HDA
- XUSB_PADCTRL
- SDHCI
- SOC_THERM
- AHUB
- I2S
- EHCI
- USB PHY

N.B. The nvidia,tegra20-timer compatible string is removed from the
nvidia,tegra30-timer.txt documentation file because it's already
mentioned in the nvidia,tegra20-timer.txt documentation file.

This second version takes into account the following requests from
Rob Herring <robherring2@gmail.com>:

- Per-IP block patches have been combined into a single patch

- Explicit documentation about which compatible strings are actually
  matched by the driver has been removed.  In its place is implicit
  documentation that loosely follows Rob's prescribed format:

  "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
   <chip> is tegra30, tegra132, ..." [...]  "You should attempt to
   document known values of <chip> if you use it"

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Dylan Reid <dgreid@chromium.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jingchang Lu <jingchang.lu@freescale.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mikko Perttunen <mperttunen@nvidia.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Peter Hurley <peter@hurleysoftware.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Tejun Heo <tj@kernel.org>
Cc: "Terje Bergström" <tbergstrom@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-pwm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Acked-by: default avatarEduardo Valentin <edubezval@gmail.com>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 2d4c0aef

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt

+4 −1
Original line number Diff line number Diff line 
NVIDIA Tegra AHB



Required properties:

- compatible : "nvidia,tegra20-ahb" or "nvidia,tegra30-ahb"

- compatible : For Tegra20, must contain "nvidia,tegra20-ahb".  For

  Tegra30, must contain "nvidia,tegra30-ahb".  Otherwise, must contain

  '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,

  tegra132, or tegra210.

- reg : Should contain 1 register ranges(address and length)



Example:

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt

+5 −1
Original line number Diff line number Diff line
@@ -6,7 +6,11 @@ modes. It provides power-gating controllers for SoC and CPU power-islands. 


Required properties:

- name : Should be pmc

- compatible : Should contain "nvidia,tegra<chip>-pmc".

- compatible : For Tegra20, must contain "nvidia,tegra20-pmc".  For Tegra30,

  must contain "nvidia,tegra30-pmc".  For Tegra114, must contain

  "nvidia,tegra114-pmc".  For Tegra124, must contain "nvidia,tegra124-pmc".

  Otherwise, must contain "nvidia,<chip>-pmc", plus at least one of the

  above, where <chip> is tegra132.

- reg : Offset and length of the register set for the device

- clocks : Must contain an entry for each entry in clock-names.

  See ../clocks/clock-bindings.txt for details.

Documentation/devicetree/bindings/ata/tegra-sata.txt

+3 −1
Original line number Diff line number Diff line 
Tegra124 SoC SATA AHCI controller



Required properties :

- compatible : "nvidia,tegra124-ahci".

- compatible : For Tegra124, must contain "nvidia,tegra124-ahci".  Otherwise,

  must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip>

  is tegra132.

- reg : Should contain 2 entries:

  - AHCI register set (SATA BAR5)

  - SATA register set

Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.txt

+5 −5
Original line number Diff line number Diff line 
NVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block.



Required properties:

- compatible : should be:

	"nvidia,tegra20-efuse"

	"nvidia,tegra30-efuse"

	"nvidia,tegra114-efuse"

	"nvidia,tegra124-efuse"

- compatible : For Tegra20, must contain "nvidia,tegra20-efuse".  For Tegra30,

  must contain "nvidia,tegra30-efuse".  For Tegra114, must contain

  "nvidia,tegra114-efuse".  For Tegra124, must contain "nvidia,tegra124-efuse".

  Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where

  <chip> is tegra132.

  Details:

  nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data

	due to a hardware bug. Tegra20 also lacks certain information which is

Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt

+6 −2
Original line number Diff line number Diff line
@@ -197,7 +197,9 @@ of the following host1x client modules: 
- sor: serial output resource



  Required properties:

  - compatible: "nvidia,tegra124-sor"

  - compatible: For Tegra124, must contain "nvidia,tegra124-sor".  Otherwise,

    must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>

    is tegra132.

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain an entry for each entry in clock-names.
@@ -222,7 +224,9 @@ of the following host1x client modules: 
  - nvidia,dpaux: phandle to a DispayPort AUX interface



- dpaux: DisplayPort AUX interface

  - compatible: "nvidia,tegra124-dpaux"

  - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux".  Otherwise,

    must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where

    <chip> is tegra132.

  - reg: Physical base address and length of the controller's registers.

  - interrupts: The interrupt outputs from the controller.

  - clocks: Must contain an entry for each entry in clock-names.