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Commit 1852c9a0 authored by Slava Grigorev's avatar Slava Grigorev Committed by Alex Deucher
Browse files

radeon/audio: moved audio packet programming to a separate function 



Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarSlava Grigorev <slava.grigorev@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent baa7d8e4

drivers/gpu/drm/radeon/dce3_1_afmt.c

+26 −30
Original line number Diff line number Diff line
@@ -199,6 +199,27 @@ void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset, 
		~HDMI0_ACR_N_48_MASK);

}



void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;



	WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,

		HDMI0_AUDIO_DELAY_EN(1) |			/* default audio delay */

		HDMI0_AUDIO_PACKETS_PER_LINE(3));	/* should be suffient for all audio modes and small enough for all hblanks */



	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,

		AFMT_AUDIO_SAMPLE_SEND |			/* send audio packets */

		AFMT_60958_CS_UPDATE);				/* allow 60958 channel status fields to be updated */



	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,

		HDMI0_AUDIO_INFO_SEND |				/* enable audio info frames (frames won't be set until audio is enabled) */

		HDMI0_AUDIO_INFO_CONT);				/* send audio info frames every frame/field */



	WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,

		HDMI0_AUDIO_INFO_LINE(2));			/* anything other than 0 */

}



/*

 * update the info frames with the data from the current display mode

 */
@@ -226,41 +247,16 @@ void dce3_1_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *m 
	radeon_audio_set_vbi_packet(encoder);

	radeon_hdmi_set_color_depth(encoder);



	if (ASIC_IS_DCE32(rdev)) {

		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,

		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */

		       HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */

		WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,

		       AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */

		       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */

	} else {

		WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,

		       HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */

		       HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */

		       HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */

		       HDMI0_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */

	}

	WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */



	if (ASIC_IS_DCE32(rdev)) {

	radeon_audio_update_acr(encoder, mode->clock);

	radeon_audio_write_speaker_allocation(encoder);

	radeon_audio_set_audio_packet(encoder);

	radeon_audio_write_sad_regs(encoder);

	}



	/* TODO: HDMI0_AUDIO_INFO_UPDATE */

	WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,

	       HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */

	       HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */



	WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,

	       HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */



	WREG32(HDMI0_GC + offset, 0); /* unset HDMI0_GC_AVMUTE */



	if (radeon_audio_set_avi_packet(encoder, mode) < 0)

		return;



	radeon_audio_update_acr(encoder, mode->clock);



	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */

	WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);

	WREG32(HDMI0_RAMP_CONTROL1 + offset, 0x007FFFFF);

drivers/gpu/drm/radeon/evergreen_hdmi.c

+42 −42
Original line number Diff line number Diff line
@@ -345,32 +345,10 @@ void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc) 
	WREG32(HDMI_CONTROL + offset, val);

}



/*

 * update the info frames with the data from the current display mode

 */

void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)

void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	uint32_t offset;



	if (!dig || !dig->afmt)

		return;



	/* Silent, r600_hdmi_enable will raise WARN for us */

	if (!dig->afmt->enabled)

		return;

	offset = dig->afmt->offset;



	/* disable audio prior to setting up hw */

	dig->afmt->pin = radeon_audio_get_pin(encoder);

	radeon_audio_enable(rdev, dig->afmt->pin, 0);



	radeon_audio_set_dto(encoder, mode->clock);

	radeon_audio_set_vbi_packet(encoder);

	radeon_hdmi_set_color_depth(encoder);



	WREG32(HDMI_INFOFRAME_CONTROL0 + offset,

		HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
@@ -382,19 +360,10 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
	WREG32(HDMI_INFOFRAME_CONTROL1 + offset,

		HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */



	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */



	WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,

		HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */

		HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */



	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,

	       AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */



	/* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */



	radeon_audio_update_acr(encoder, mode->clock);



	WREG32(AFMT_60958_0 + offset,

		AFMT_60958_CS_CHANNEL_NUMBER_L(1));
@@ -409,12 +378,46 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
		AFMT_60958_CS_CHANNEL_NUMBER_6(7) |

		AFMT_60958_CS_CHANNEL_NUMBER_7(8));



	radeon_audio_write_speaker_allocation(encoder);



	WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,

		AFMT_AUDIO_CHANNEL_ENABLE(0xff));



	/* fglrx sets 0x40 in 0x5f80 here */

	/* allow 60958 channel status and send audio packets fields to be updated */

	WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,

		AFMT_AUDIO_SAMPLE_SEND | AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE);

}



/*

 * update the info frames with the data from the current display mode

 */

void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	uint32_t offset;



	if (!dig || !dig->afmt)

		return;



	/* Silent, r600_hdmi_enable will raise WARN for us */

	if (!dig->afmt->enabled)

		return;

	offset = dig->afmt->offset;



	/* disable audio prior to setting up hw */

	dig->afmt->pin = radeon_audio_get_pin(encoder);

	radeon_audio_enable(rdev, dig->afmt->pin, 0);



	radeon_audio_set_dto(encoder, mode->clock);

	radeon_audio_set_vbi_packet(encoder);

	radeon_hdmi_set_color_depth(encoder);



	WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */



	radeon_audio_update_acr(encoder, mode->clock);

	radeon_audio_write_speaker_allocation(encoder);

	radeon_audio_set_audio_packet(encoder);



	radeon_audio_select_pin(encoder);

	radeon_audio_write_sad_regs(encoder);
@@ -423,9 +426,6 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode 
	if (radeon_audio_set_avi_packet(encoder, mode) < 0)

		return;



	WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,

		  AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */



	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */

	WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);

	WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);

drivers/gpu/drm/radeon/r600_hdmi.c

+45 −40
Original line number Diff line number Diff line
@@ -347,32 +347,10 @@ void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset) 
		HDMI0_GC_CONT);		/* send general control packets every frame */

}



/*

 * update the info frames with the data from the current display mode

 */

void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)

void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	uint32_t offset;



	if (!dig || !dig->afmt)

		return;



	/* Silent, r600_hdmi_enable will raise WARN for us */

	if (!dig->afmt->enabled)

		return;

	offset = dig->afmt->offset;



	/* disable audio prior to setting up hw */

	dig->afmt->pin = radeon_audio_get_pin(encoder);

	radeon_audio_enable(rdev, dig->afmt->pin, 0);



	radeon_audio_set_dto(encoder, mode->clock);

	radeon_audio_set_vbi_packet(encoder);

	radeon_hdmi_set_color_depth(encoder);



	WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset,

		HDMI0_AUDIO_SAMPLE_SEND |			/* send audio packets */
@@ -392,14 +370,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod 
		HDMI0_AUDIO_INFO_LINE(2),	/* anything other than 0 */

		~HDMI0_AUDIO_INFO_LINE_MASK);



	WREG32_AND(HDMI0_GC + offset,

		   ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */



	if (radeon_audio_set_avi_packet(encoder, mode) < 0)

		return;



	/* fglrx duplicates INFOFRAME_CONTROL0 & INFOFRAME_CONTROL1 ops here */



	WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset,

		~(HDMI0_GENERIC0_SEND |

		HDMI0_GENERIC0_CONT |
@@ -409,8 +379,6 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod 
		HDMI0_GENERIC0_LINE_MASK |

		HDMI0_GENERIC1_LINE_MASK));



	radeon_audio_update_acr(encoder, mode->clock);



	WREG32_P(HDMI0_60958_0 + offset,

		HDMI0_60958_CS_CHANNEL_NUMBER_L(1),

		~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK |
@@ -419,6 +387,43 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod 
	WREG32_P(HDMI0_60958_1 + offset,

		HDMI0_60958_CS_CHANNEL_NUMBER_R(2),

		~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK);

}



/*

 * update the info frames with the data from the current display mode

 */

void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)

{

	struct drm_device *dev = encoder->dev;

	struct radeon_device *rdev = dev->dev_private;

	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;

	uint32_t offset;



	if (!dig || !dig->afmt)

		return;



	/* Silent, r600_hdmi_enable will raise WARN for us */

	if (!dig->afmt->enabled)

		return;

	offset = dig->afmt->offset;



	/* disable audio prior to setting up hw */

	dig->afmt->pin = radeon_audio_get_pin(encoder);

	radeon_audio_enable(rdev, dig->afmt->pin, 0);



	radeon_audio_set_dto(encoder, mode->clock);

	radeon_audio_set_vbi_packet(encoder);

	radeon_hdmi_set_color_depth(encoder);



	WREG32_AND(HDMI0_GC + offset,

		   ~HDMI0_GC_AVMUTE); /* unset HDMI0_GC_AVMUTE */



	radeon_audio_update_acr(encoder, mode->clock);

	radeon_audio_set_audio_packet(encoder);



	if (radeon_audio_set_avi_packet(encoder, mode) < 0)

		return;



	/* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */

	WREG32(HDMI0_RAMP_CONTROL0 + offset, 0x00FFFFFF);

drivers/gpu/drm/radeon/radeon_audio.c

+19 −0
Original line number Diff line number Diff line
@@ -89,6 +89,9 @@ void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset); 
void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset);

void dce4_hdmi_set_color_depth(struct drm_encoder *encoder,

	u32 offset, int bpc);

void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset);

void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset);

void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset);



static const u32 pin_offsets[7] =

{
@@ -142,6 +145,7 @@ static struct radeon_audio_funcs r600_hdmi_funcs = { 
	.update_acr = r600_hdmi_update_acr,

	.set_vbi_packet = r600_set_vbi_packet,

	.set_avi_packet = r600_set_avi_packet,

	.set_audio_packet = r600_set_audio_packet,

};



static struct radeon_audio_funcs dce32_hdmi_funcs = {
@@ -152,6 +156,7 @@ static struct radeon_audio_funcs dce32_hdmi_funcs = { 
	.update_acr = dce3_2_hdmi_update_acr,

	.set_vbi_packet = r600_set_vbi_packet,

	.set_avi_packet = r600_set_avi_packet,

	.set_audio_packet = dce3_2_set_audio_packet,

};



static struct radeon_audio_funcs dce32_dp_funcs = {
@@ -172,6 +177,7 @@ static struct radeon_audio_funcs dce4_hdmi_funcs = { 
	.set_vbi_packet = dce4_set_vbi_packet,

	.set_color_depth = dce4_hdmi_set_color_depth,

	.set_avi_packet = evergreen_set_avi_packet,

	.set_audio_packet = dce4_set_audio_packet,

};



static struct radeon_audio_funcs dce4_dp_funcs = {
@@ -194,6 +200,7 @@ static struct radeon_audio_funcs dce6_hdmi_funcs = { 
	.set_vbi_packet = dce4_set_vbi_packet,

	.set_color_depth = dce4_hdmi_set_color_depth,

	.set_avi_packet = evergreen_set_avi_packet,

	.set_audio_packet = dce4_set_audio_packet,

};



static struct radeon_audio_funcs dce6_dp_funcs = {
@@ -617,3 +624,15 @@ void radeon_hdmi_set_color_depth(struct drm_encoder *encoder) 
	if (radeon_encoder->audio && radeon_encoder->audio->set_color_depth)

		radeon_encoder->audio->set_color_depth(encoder, dig->afmt->offset, bpc);

}



void radeon_audio_set_audio_packet(struct drm_encoder *encoder)

{

    struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);

    struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;



	if (!dig || !dig->afmt)

		return;



	if (radeon_encoder->audio && radeon_encoder->audio->set_audio_packet)

		radeon_encoder->audio->set_audio_packet(encoder, dig->afmt->offset);

}

drivers/gpu/drm/radeon/radeon_audio.h

+2 −0
Original line number Diff line number Diff line
@@ -59,6 +59,7 @@ struct radeon_audio_funcs 
	void (*set_color_depth)(struct drm_encoder *encoder, u32 offset, int bpc);

	void (*set_avi_packet)(struct radeon_device *rdev, u32 offset,

		unsigned char *buffer, size_t size);

	void (*set_audio_packet)(struct drm_encoder *encoder, u32 offset);

};



int radeon_audio_init(struct radeon_device *rdev);
@@ -83,5 +84,6 @@ int radeon_audio_set_avi_packet(struct drm_encoder *encoder, 
void radeon_audio_update_acr(struct drm_encoder *encoder, unsigned int clock);

void radeon_audio_set_vbi_packet(struct drm_encoder *encoder);

void radeon_hdmi_set_color_depth(struct drm_encoder *encoder);

void radeon_audio_set_audio_packet(struct drm_encoder *encoder);



#endif