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Commit 18408da0 authored by Aaro Koskinen's avatar Aaro Koskinen Committed by Greg Kroah-Hartman
Browse files

staging: xgifb: drop XG41 code 



XG_41 is not listed in xgifb_pci_table, so the code can be safely dropped.

Signed-off-by: default avatarAaro Koskinen <aaro.koskinen@iki.fi>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent aca03bcc

drivers/staging/xgifb/XGI_main.h

+0 −3
Original line number Diff line number Diff line
@@ -12,9 +12,6 @@ 


#define XGIFAIL(x) do { printk(x "\n"); return -EINVAL; } while (0)



#ifndef PCI_DEVICE_ID_XGI_41

#define PCI_DEVICE_ID_XGI_41      0x041

#endif

#ifndef PCI_DEVICE_ID_XGI_42

#define PCI_DEVICE_ID_XGI_42      0x042

#endif

drivers/staging/xgifb/XGI_main_26.c

+0 −3
Original line number Diff line number Diff line
@@ -1924,9 +1924,6 @@ static int __devinit xgifb_probe(struct pci_dev *pdev, 
	case PCI_DEVICE_ID_XGI_40:

		xgifb_info->chip = XG40;

		break;

	case PCI_DEVICE_ID_XGI_41:

		xgifb_info->chip = XG41;

		break;

	case PCI_DEVICE_ID_XGI_42:

		xgifb_info->chip = XG42;

		break;

drivers/staging/xgifb/XGIfb.h

+0 −1
Original line number Diff line number Diff line
@@ -23,7 +23,6 @@ enum xgifb_display_type { 


enum XGI_CHIP_TYPE {

	XG40 = 32,

	XG41,

	XG42,

	XG45,

	XG20 = 48,

drivers/staging/xgifb/vb_init.c

+1 −75
Original line number Diff line number Diff line
@@ -353,7 +353,6 @@ static void XGINew_DDR1x_DefaultRegister( 
		XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);



		switch (HwDeviceExtension->jChipType) {

		case XG41:

		case XG42:

			/* CR82 */

			xgifb_reg_set(P3d4,
@@ -556,8 +555,7 @@ static void XGINew_SetDRAMDefaultRegister340( 
		xgifb_reg_set(P3d4, (0x8A + j),

				pVBInfo->CR40[1 + j][pVBInfo->ram_type]);



	if ((HwDeviceExtension->jChipType == XG41) ||

	    (HwDeviceExtension->jChipType == XG42))

	if (HwDeviceExtension->jChipType == XG42)

		xgifb_reg_set(P3d4, 0x8C, 0x87);



	xgifb_reg_set(P3d4,
@@ -854,78 +852,6 @@ static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension, 
		pVBInfo->ram_channel = 1; /* Single channel */

		xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/

		break;

	case XG41:

		if (XGINew_CheckFrequence(pVBInfo) == 1) {

			pVBInfo->ram_bus = 32; /* 32 bits */

			pVBInfo->ram_channel = 3; /* Quad Channel */

			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);

			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);



			if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)

				return;



			pVBInfo->ram_channel = 2; /* Dual channels */

			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);



			if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)

				return;



			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);



			if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)

				return;



			pVBInfo->ram_channel = 3;

			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);

			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);



			if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)

				return;



			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);



			if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)

				return;

			else

				xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);

		} else { /* DDR */

			pVBInfo->ram_bus = 64; /* 64 bits */

			pVBInfo->ram_channel = 2; /* Dual channels */

			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);

			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);



			if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)

				return;



			pVBInfo->ram_channel = 1; /* Single channels */

			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);



			if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)

				return;



			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);



			if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)

				return;



			pVBInfo->ram_channel = 2; /* Dual channels */

			xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);

			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);



			if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)

				return;



			pVBInfo->ram_channel = 1; /* Single channels */

			xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);



			if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)

				return;

			else

				xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);

		}



		break;



	case XG42:

		/*

		 XG42 SR14 D[3] Reserve