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Commit 17d18b44 authored by Puranam V G Tejaswi's avatar Puranam V G Tejaswi
Browse files

msm: kgsl: Use correct Highest Bank Bit (HBB) value for LPDDR3 on A702 



LPDDR3 provides multiple config options based on DDR density. The HBB
values are different for various config options. As A702 supports LPDDR3,
query for the appropriate HBB value from device tree for LPDDR3 parts.

Change-Id: I60b469363636985963ada007f43196aa25608267
Signed-off-by: default avatarPuranam V G Tejaswi <pvgtejas@codeaurora.org>
parent 4d86e041

drivers/gpu/msm/adreno_a6xx.c

+2 −1
Original line number Diff line number Diff line
@@ -150,7 +150,8 @@ static void a6xx_init(struct adreno_device *adreno_dev) 
	/* LP DDR4 highest bank bit is different and needs to be overridden */

	if (adreno_is_a650(adreno_dev) && of_fdt_get_ddrtype() == 0x7)

		adreno_dev->highest_bank_bit = 15;

	else if (adreno_is_a610(adreno_dev) && of_fdt_get_ddrtype() == 0x5) {

	else if ((adreno_is_a610(adreno_dev) || adreno_is_a702(adreno_dev))

			&& of_fdt_get_ddrtype() == 0x5) {

		/*

		 * LPDDR3 has multiple different highest bank bit value

		 * based on different DDR density. Query this value from