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Commit 17aa6be9 authored by Daniel Vetter's avatar Daniel Vetter
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drm/i915: simplify DP/DDI port width macros 



If we ever leak a non-DP compliant port width through here, we have a
pretty serious issue. So just rip out all these WARNs - if we need
them it's probably better to have them at a central place where we
compute the dp lane count.

Also use the new DDI width macro for FDI mode.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: fixup the embarrassing s/intel_dp->DP/temp/ mistake Paulo
spotted.]
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent dce3271b

drivers/gpu/drm/i915/i915_reg.h

+2 −9
Original line number Original line Diff line number Diff line
@@ -2664,9 +2664,7 @@ 
#define   DP_PRE_EMPHASIS_SHIFT		22

#define   DP_PRE_EMPHASIS_SHIFT		22





/* How many wires to use. I guess 3 was too hard */

/* How many wires to use. I guess 3 was too hard */

#define   DP_PORT_WIDTH_1		(0 << 19)

#define   DP_PORT_WIDTH(width)		(((width) - 1) << 19)

#define   DP_PORT_WIDTH_2		(1 << 19)

#define   DP_PORT_WIDTH_4		(3 << 19)

#define   DP_PORT_WIDTH_MASK		(7 << 19)

#define   DP_PORT_WIDTH_MASK		(7 << 19)





/* Mystic DPCD version 1.1 special mode */

/* Mystic DPCD version 1.1 special mode */
@@ -4755,9 +4753,6 @@ 
#define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)

#define  TRANS_DDI_EDP_INPUT_B_ONOFF	(5<<12)

#define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)

#define  TRANS_DDI_EDP_INPUT_C_ONOFF	(6<<12)

#define  TRANS_DDI_BFI_ENABLE		(1<<4)

#define  TRANS_DDI_BFI_ENABLE		(1<<4)

#define  TRANS_DDI_PORT_WIDTH_X1	(0<<1)

#define  TRANS_DDI_PORT_WIDTH_X2	(1<<1)

#define  TRANS_DDI_PORT_WIDTH_X4	(3<<1)





/* DisplayPort Transport Control */

/* DisplayPort Transport Control */

#define DP_TP_CTL_A			0x64040

#define DP_TP_CTL_A			0x64040
@@ -4801,9 +4796,7 @@ 
#define  DDI_BUF_PORT_REVERSAL			(1<<16)

#define  DDI_BUF_PORT_REVERSAL			(1<<16)

#define  DDI_BUF_IS_IDLE			(1<<7)

#define  DDI_BUF_IS_IDLE			(1<<7)

#define  DDI_A_4_LANES				(1<<4)

#define  DDI_A_4_LANES				(1<<4)

#define  DDI_PORT_WIDTH_X1			(0<<1)

#define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)

#define  DDI_PORT_WIDTH_X2			(1<<1)

#define  DDI_PORT_WIDTH_X4			(3<<1)

#define  DDI_INIT_DISPLAY_DETECTED		(1<<0)

#define  DDI_INIT_DISPLAY_DETECTED		(1<<0)





/* DDI Buffer Translations */

/* DDI Buffer Translations */

drivers/gpu/drm/i915/intel_ddi.c

+2 −32
Original line number Original line Diff line number Diff line
@@ -687,22 +687,7 @@ static void intel_ddi_mode_set(struct drm_encoder *encoder, 




		intel_dp->DP = intel_dig_port->port_reversal |

		intel_dp->DP = intel_dig_port->port_reversal |

			       DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;

			       DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW;

		switch (intel_dp->lane_count) {

		intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);

		case 1:

			intel_dp->DP |= DDI_PORT_WIDTH_X1;

			break;

		case 2:

			intel_dp->DP |= DDI_PORT_WIDTH_X2;

			break;

		case 4:

			intel_dp->DP |= DDI_PORT_WIDTH_X4;

			break;

		default:

			intel_dp->DP |= DDI_PORT_WIDTH_X4;

			WARN(1, "Unexpected DP lane count %d\n",

			     intel_dp->lane_count);

			break;

		}





		if (intel_dp->has_audio) {

		if (intel_dp->has_audio) {

			DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",

			DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
@@ -1031,22 +1016,7 @@ void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 




		temp |= TRANS_DDI_MODE_SELECT_DP_SST;

		temp |= TRANS_DDI_MODE_SELECT_DP_SST;





		switch (intel_dp->lane_count) {

		temp |= DDI_PORT_WIDTH(intel_dp->lane_count);

		case 1:

			temp |= TRANS_DDI_PORT_WIDTH_X1;

			break;

		case 2:

			temp |= TRANS_DDI_PORT_WIDTH_X2;

			break;

		case 4:

			temp |= TRANS_DDI_PORT_WIDTH_X4;

			break;

		default:

			temp |= TRANS_DDI_PORT_WIDTH_X4;

			WARN(1, "Unsupported lane count %d\n",

			     intel_dp->lane_count);

		}



	} else {

	} else {

		WARN(1, "Invalid encoder type %d for pipe %c\n",

		WARN(1, "Invalid encoder type %d for pipe %c\n",

		     intel_encoder->type, pipe_name(pipe));

		     intel_encoder->type, pipe_name(pipe));

drivers/gpu/drm/i915/intel_dp.c

+1 −11
Original line number Original line Diff line number Diff line
@@ -891,18 +891,8 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 




	/* Handle DP bits in common between all three register formats */

	/* Handle DP bits in common between all three register formats */

	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;

	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);





	switch (intel_dp->lane_count) {

	case 1:

		intel_dp->DP |= DP_PORT_WIDTH_1;

		break;

	case 2:

		intel_dp->DP |= DP_PORT_WIDTH_2;

		break;

	case 4:

		intel_dp->DP |= DP_PORT_WIDTH_4;

		break;

	}

	if (intel_dp->has_audio) {

	if (intel_dp->has_audio) {

		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",

		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",

				 pipe_name(intel_crtc->pipe));

				 pipe_name(intel_crtc->pipe));