drm/nouveau/clk: allow fb to signal it needs to do a multi-stage reclock (1789cab4) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/gpu/drm/nouveau/core/subdev/clock/base.c

+6 −3

Original line number	Diff line number	Diff line
		@@ -182,9 +182,12 @@ nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
		clk->pstate = pstatei;

		if (pfb->ram->calc) {
		ret = pfb->ram->calc(pfb, pstate->base.domain[nv_clk_src_mem]);
		int khz = pstate->base.domain[nv_clk_src_mem];
		do {
		ret = pfb->ram->calc(pfb, khz);
		if (ret == 0)
		ret = pfb->ram->prog(pfb);
		} while (ret > 0);
		pfb->ram->tidy(pfb);
		}