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Commit 16a7989a authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Drop print_status callbacks. 



First patch in series to move to user mode
debug tools we're removing the print_status callbacks.

These functions were unused at the moment anyway.

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a72d5604

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c

+0 −8
Original line number Diff line number Diff line
@@ -463,13 +463,6 @@ static int acp_soft_reset(void *handle) 
	return 0;

}



static void acp_print_status(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	dev_info(adev->dev, "ACP STATUS\n");

}



static int acp_set_clockgating_state(void *handle,

				     enum amd_clockgating_state state)

{
@@ -494,7 +487,6 @@ const struct amd_ip_funcs acp_ip_funcs = { 
	.is_idle = acp_is_idle,

	.wait_for_idle = acp_wait_for_idle,

	.soft_reset = acp_soft_reset,

	.print_status = acp_print_status,

	.set_clockgating_state = acp_set_clockgating_state,

	.set_powergating_state = acp_set_powergating_state,

};

drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c

+0 −10
Original line number Diff line number Diff line
@@ -303,15 +303,6 @@ static int amdgpu_pp_soft_reset(void *handle) 
	return ret;

}



static void amdgpu_pp_print_status(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	if (adev->powerplay.ip_funcs->print_status)

		adev->powerplay.ip_funcs->print_status(

					adev->powerplay.pp_handle);

}



const struct amd_ip_funcs amdgpu_pp_ip_funcs = {

	.early_init = amdgpu_pp_early_init,

	.late_init = amdgpu_pp_late_init,
@@ -324,7 +315,6 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = { 
	.is_idle = amdgpu_pp_is_idle,

	.wait_for_idle = amdgpu_pp_wait_for_idle,

	.soft_reset = amdgpu_pp_soft_reset,

	.print_status = amdgpu_pp_print_status,

	.set_clockgating_state = amdgpu_pp_set_clockgating_state,

	.set_powergating_state = amdgpu_pp_set_powergating_state,

};

drivers/gpu/drm/amd/amdgpu/ci_dpm.c

+0 −210
Original line number Diff line number Diff line
@@ -6309,215 +6309,6 @@ static int ci_dpm_wait_for_idle(void *handle) 
	return 0;

}



static void ci_dpm_print_status(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	dev_info(adev->dev, "CIK DPM registers\n");

	dev_info(adev->dev, "  BIOS_SCRATCH_4=0x%08X\n",

		 RREG32(mmBIOS_SCRATCH_4));

	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING=0x%08X\n",

		 RREG32(mmMC_ARB_DRAM_TIMING));

	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING2=0x%08X\n",

		 RREG32(mmMC_ARB_DRAM_TIMING2));

	dev_info(adev->dev, "  MC_ARB_BURST_TIME=0x%08X\n",

		 RREG32(mmMC_ARB_BURST_TIME));

	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING_1=0x%08X\n",

		 RREG32(mmMC_ARB_DRAM_TIMING_1));

	dev_info(adev->dev, "  MC_ARB_DRAM_TIMING2_1=0x%08X\n",

		 RREG32(mmMC_ARB_DRAM_TIMING2_1));

	dev_info(adev->dev, "  MC_CG_CONFIG=0x%08X\n",

		 RREG32(mmMC_CG_CONFIG));

	dev_info(adev->dev, "  MC_ARB_CG=0x%08X\n",

		 RREG32(mmMC_ARB_CG));

	dev_info(adev->dev, "  DIDT_SQ_CTRL0=0x%08X\n",

		 RREG32_DIDT(ixDIDT_SQ_CTRL0));

	dev_info(adev->dev, "  DIDT_DB_CTRL0=0x%08X\n",

		 RREG32_DIDT(ixDIDT_DB_CTRL0));

	dev_info(adev->dev, "  DIDT_TD_CTRL0=0x%08X\n",

		 RREG32_DIDT(ixDIDT_TD_CTRL0));

	dev_info(adev->dev, "  DIDT_TCP_CTRL0=0x%08X\n",

		 RREG32_DIDT(ixDIDT_TCP_CTRL0));

	dev_info(adev->dev, "  CG_THERMAL_INT=0x%08X\n",

		 RREG32_SMC(ixCG_THERMAL_INT));

	dev_info(adev->dev, "  CG_THERMAL_CTRL=0x%08X\n",

		 RREG32_SMC(ixCG_THERMAL_CTRL));

	dev_info(adev->dev, "  GENERAL_PWRMGT=0x%08X\n",

		 RREG32_SMC(ixGENERAL_PWRMGT));

	dev_info(adev->dev, "  MC_SEQ_CNTL_3=0x%08X\n",

		 RREG32(mmMC_SEQ_CNTL_3));

	dev_info(adev->dev, "  LCAC_MC0_CNTL=0x%08X\n",

		 RREG32_SMC(ixLCAC_MC0_CNTL));

	dev_info(adev->dev, "  LCAC_MC1_CNTL=0x%08X\n",

		 RREG32_SMC(ixLCAC_MC1_CNTL));

	dev_info(adev->dev, "  LCAC_CPL_CNTL=0x%08X\n",

		 RREG32_SMC(ixLCAC_CPL_CNTL));

	dev_info(adev->dev, "  SCLK_PWRMGT_CNTL=0x%08X\n",

		 RREG32_SMC(ixSCLK_PWRMGT_CNTL));

	dev_info(adev->dev, "  BIF_LNCNT_RESET=0x%08X\n",

		 RREG32(mmBIF_LNCNT_RESET));

	dev_info(adev->dev, "  FIRMWARE_FLAGS=0x%08X\n",

		 RREG32_SMC(ixFIRMWARE_FLAGS));

	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL=0x%08X\n",

		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL));

	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_2=0x%08X\n",

		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2));

	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_3=0x%08X\n",

		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3));

	dev_info(adev->dev, "  CG_SPLL_FUNC_CNTL_4=0x%08X\n",

		 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4));

	dev_info(adev->dev, "  CG_SPLL_SPREAD_SPECTRUM=0x%08X\n",

		 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM));

	dev_info(adev->dev, "  CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n",

		 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2));

	dev_info(adev->dev, "  DLL_CNTL=0x%08X\n",

		 RREG32(mmDLL_CNTL));

	dev_info(adev->dev, "  MCLK_PWRMGT_CNTL=0x%08X\n",

		 RREG32(mmMCLK_PWRMGT_CNTL));

	dev_info(adev->dev, "  MPLL_AD_FUNC_CNTL=0x%08X\n",

		 RREG32(mmMPLL_AD_FUNC_CNTL));

	dev_info(adev->dev, "  MPLL_DQ_FUNC_CNTL=0x%08X\n",

		 RREG32(mmMPLL_DQ_FUNC_CNTL));

	dev_info(adev->dev, "  MPLL_FUNC_CNTL=0x%08X\n",

		 RREG32(mmMPLL_FUNC_CNTL));

	dev_info(adev->dev, "  MPLL_FUNC_CNTL_1=0x%08X\n",

		 RREG32(mmMPLL_FUNC_CNTL_1));

	dev_info(adev->dev, "  MPLL_FUNC_CNTL_2=0x%08X\n",

		 RREG32(mmMPLL_FUNC_CNTL_2));

	dev_info(adev->dev, "  MPLL_SS1=0x%08X\n",

		 RREG32(mmMPLL_SS1));

	dev_info(adev->dev, "  MPLL_SS2=0x%08X\n",

		 RREG32(mmMPLL_SS2));

	dev_info(adev->dev, "  CG_DISPLAY_GAP_CNTL=0x%08X\n",

		 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL));

	dev_info(adev->dev, "  CG_DISPLAY_GAP_CNTL2=0x%08X\n",

		 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2));

	dev_info(adev->dev, "  CG_STATIC_SCREEN_PARAMETER=0x%08X\n",

		 RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER));

	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_0=0x%08X\n",

		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));

	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_1=0x%08X\n",

		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1));

	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_2=0x%08X\n",

		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2));

	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_3=0x%08X\n",

		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3));

	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_4=0x%08X\n",

		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4));

	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_5=0x%08X\n",

		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5));

	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_6=0x%08X\n",

		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6));

	dev_info(adev->dev, "  CG_FREQ_TRAN_VOTING_7=0x%08X\n",

		 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7));

	dev_info(adev->dev, "  RCU_UC_EVENTS=0x%08X\n",

		 RREG32_SMC(ixRCU_UC_EVENTS));

	dev_info(adev->dev, "  DPM_TABLE_475=0x%08X\n",

		 RREG32_SMC(ixDPM_TABLE_475));

	dev_info(adev->dev, "  MC_SEQ_RAS_TIMING_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_RAS_TIMING_LP));

	dev_info(adev->dev, "  MC_SEQ_RAS_TIMING=0x%08X\n",

		 RREG32(mmMC_SEQ_RAS_TIMING));

	dev_info(adev->dev, "  MC_SEQ_CAS_TIMING_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_CAS_TIMING_LP));

	dev_info(adev->dev, "  MC_SEQ_CAS_TIMING=0x%08X\n",

		 RREG32(mmMC_SEQ_CAS_TIMING));

	dev_info(adev->dev, "  MC_SEQ_DLL_STBY_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_DLL_STBY_LP));

	dev_info(adev->dev, "  MC_SEQ_DLL_STBY=0x%08X\n",

		 RREG32(mmMC_SEQ_DLL_STBY));

	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD0_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_G5PDX_CMD0_LP));

	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD0=0x%08X\n",

		 RREG32(mmMC_SEQ_G5PDX_CMD0));

	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD1_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_G5PDX_CMD1_LP));

	dev_info(adev->dev, "  MC_SEQ_G5PDX_CMD1=0x%08X\n",

		 RREG32(mmMC_SEQ_G5PDX_CMD1));

	dev_info(adev->dev, "  MC_SEQ_G5PDX_CTRL_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_G5PDX_CTRL_LP));

	dev_info(adev->dev, "  MC_SEQ_G5PDX_CTRL=0x%08X\n",

		 RREG32(mmMC_SEQ_G5PDX_CTRL));

	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_PMG_DVS_CMD_LP));

	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CMD=0x%08X\n",

		 RREG32(mmMC_SEQ_PMG_DVS_CMD));

	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_PMG_DVS_CTL_LP));

	dev_info(adev->dev, "  MC_SEQ_PMG_DVS_CTL=0x%08X\n",

		 RREG32(mmMC_SEQ_PMG_DVS_CTL));

	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_MISC_TIMING_LP));

	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING=0x%08X\n",

		 RREG32(mmMC_SEQ_MISC_TIMING));

	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING2_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_MISC_TIMING2_LP));

	dev_info(adev->dev, "  MC_SEQ_MISC_TIMING2=0x%08X\n",

		 RREG32(mmMC_SEQ_MISC_TIMING2));

	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP));

	dev_info(adev->dev, "  MC_PMG_CMD_EMRS=0x%08X\n",

		 RREG32(mmMC_PMG_CMD_EMRS));

	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_PMG_CMD_MRS_LP));

	dev_info(adev->dev, "  MC_PMG_CMD_MRS=0x%08X\n",

		 RREG32(mmMC_PMG_CMD_MRS));

	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP));

	dev_info(adev->dev, "  MC_PMG_CMD_MRS1=0x%08X\n",

		 RREG32(mmMC_PMG_CMD_MRS1));

	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D0_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_WR_CTL_D0_LP));

	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D0=0x%08X\n",

		 RREG32(mmMC_SEQ_WR_CTL_D0));

	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D1_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_WR_CTL_D1_LP));

	dev_info(adev->dev, "  MC_SEQ_WR_CTL_D1=0x%08X\n",

		 RREG32(mmMC_SEQ_WR_CTL_D1));

	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D0_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_RD_CTL_D0_LP));

	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D0=0x%08X\n",

		 RREG32(mmMC_SEQ_RD_CTL_D0));

	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D1_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_RD_CTL_D1_LP));

	dev_info(adev->dev, "  MC_SEQ_RD_CTL_D1=0x%08X\n",

		 RREG32(mmMC_SEQ_RD_CTL_D1));

	dev_info(adev->dev, "  MC_SEQ_PMG_TIMING_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_PMG_TIMING_LP));

	dev_info(adev->dev, "  MC_SEQ_PMG_TIMING=0x%08X\n",

		 RREG32(mmMC_SEQ_PMG_TIMING));

	dev_info(adev->dev, "  MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP));

	dev_info(adev->dev, "  MC_PMG_CMD_MRS2=0x%08X\n",

		 RREG32(mmMC_PMG_CMD_MRS2));

	dev_info(adev->dev, "  MC_SEQ_WR_CTL_2_LP=0x%08X\n",

		 RREG32(mmMC_SEQ_WR_CTL_2_LP));

	dev_info(adev->dev, "  MC_SEQ_WR_CTL_2=0x%08X\n",

		 RREG32(mmMC_SEQ_WR_CTL_2));

	dev_info(adev->dev, "  PCIE_LC_SPEED_CNTL=0x%08X\n",

		 RREG32_PCIE(ixPCIE_LC_SPEED_CNTL));

	dev_info(adev->dev, "  PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n",

		 RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL));

	dev_info(adev->dev, "  SMC_IND_INDEX_0=0x%08X\n",

		 RREG32(mmSMC_IND_INDEX_0));

	dev_info(adev->dev, "  SMC_IND_DATA_0=0x%08X\n",

		 RREG32(mmSMC_IND_DATA_0));

	dev_info(adev->dev, "  SMC_IND_ACCESS_CNTL=0x%08X\n",

		 RREG32(mmSMC_IND_ACCESS_CNTL));

	dev_info(adev->dev, "  SMC_RESP_0=0x%08X\n",

		 RREG32(mmSMC_RESP_0));

	dev_info(adev->dev, "  SMC_MESSAGE_0=0x%08X\n",

		 RREG32(mmSMC_MESSAGE_0));

	dev_info(adev->dev, "  SMC_SYSCON_RESET_CNTL=0x%08X\n",

		 RREG32_SMC(ixSMC_SYSCON_RESET_CNTL));

	dev_info(adev->dev, "  SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n",

		 RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0));

	dev_info(adev->dev, "  SMC_SYSCON_MISC_CNTL=0x%08X\n",

		 RREG32_SMC(ixSMC_SYSCON_MISC_CNTL));

	dev_info(adev->dev, "  SMC_PC_C=0x%08X\n",

		 RREG32_SMC(ixSMC_PC_C));

}



static int ci_dpm_soft_reset(void *handle)

{

	return 0;
@@ -6625,7 +6416,6 @@ const struct amd_ip_funcs ci_dpm_ip_funcs = { 
	.is_idle = ci_dpm_is_idle,

	.wait_for_idle = ci_dpm_wait_for_idle,

	.soft_reset = ci_dpm_soft_reset,

	.print_status = ci_dpm_print_status,

	.set_clockgating_state = ci_dpm_set_clockgating_state,

	.set_powergating_state = ci_dpm_set_powergating_state,

};

drivers/gpu/drm/amd/amdgpu/cik.c

+0 −6
Original line number Diff line number Diff line
@@ -2214,11 +2214,6 @@ static int cik_common_wait_for_idle(void *handle) 
	return 0;

}



static void cik_common_print_status(void *handle)

{



}



static int cik_common_soft_reset(void *handle)

{

	/* XXX hard reset?? */
@@ -2249,7 +2244,6 @@ const struct amd_ip_funcs cik_common_ip_funcs = { 
	.is_idle = cik_common_is_idle,

	.wait_for_idle = cik_common_wait_for_idle,

	.soft_reset = cik_common_soft_reset,

	.print_status = cik_common_print_status,

	.set_clockgating_state = cik_common_set_clockgating_state,

	.set_powergating_state = cik_common_set_powergating_state,

};

drivers/gpu/drm/amd/amdgpu/cik_ih.c

+0 −34
Original line number Diff line number Diff line
@@ -372,35 +372,6 @@ static int cik_ih_wait_for_idle(void *handle) 
	return -ETIMEDOUT;

}



static void cik_ih_print_status(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	dev_info(adev->dev, "CIK IH registers\n");

	dev_info(adev->dev, "  SRBM_STATUS=0x%08X\n",

		RREG32(mmSRBM_STATUS));

	dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",

		RREG32(mmSRBM_STATUS2));

	dev_info(adev->dev, "  INTERRUPT_CNTL=0x%08X\n",

		 RREG32(mmINTERRUPT_CNTL));

	dev_info(adev->dev, "  INTERRUPT_CNTL2=0x%08X\n",

		 RREG32(mmINTERRUPT_CNTL2));

	dev_info(adev->dev, "  IH_CNTL=0x%08X\n",

		 RREG32(mmIH_CNTL));

	dev_info(adev->dev, "  IH_RB_CNTL=0x%08X\n",

		 RREG32(mmIH_RB_CNTL));

	dev_info(adev->dev, "  IH_RB_BASE=0x%08X\n",

		 RREG32(mmIH_RB_BASE));

	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_LO=0x%08X\n",

		 RREG32(mmIH_RB_WPTR_ADDR_LO));

	dev_info(adev->dev, "  IH_RB_WPTR_ADDR_HI=0x%08X\n",

		 RREG32(mmIH_RB_WPTR_ADDR_HI));

	dev_info(adev->dev, "  IH_RB_RPTR=0x%08X\n",

		 RREG32(mmIH_RB_RPTR));

	dev_info(adev->dev, "  IH_RB_WPTR=0x%08X\n",

		 RREG32(mmIH_RB_WPTR));

}



static int cik_ih_soft_reset(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -412,8 +383,6 @@ static int cik_ih_soft_reset(void *handle) 
		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;



	if (srbm_soft_reset) {

		cik_ih_print_status((void *)adev);



		tmp = RREG32(mmSRBM_SOFT_RESET);

		tmp |= srbm_soft_reset;

		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -428,8 +397,6 @@ static int cik_ih_soft_reset(void *handle) 


		/* Wait a little for things to settle down */

		udelay(50);



		cik_ih_print_status((void *)adev);

	}



	return 0;
@@ -459,7 +426,6 @@ const struct amd_ip_funcs cik_ih_ip_funcs = { 
	.is_idle = cik_ih_is_idle,

	.wait_for_idle = cik_ih_wait_for_idle,

	.soft_reset = cik_ih_soft_reset,

	.print_status = cik_ih_print_status,

	.set_clockgating_state = cik_ih_set_clockgating_state,

	.set_powergating_state = cik_ih_set_powergating_state,

};