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Commit 16757cbc authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-cleanup-for-v4.7' of... 

Merge tag 'renesas-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC Cleanup for v4.7

* Remove unnecessary clock-output-names properties from DT
* Use generic pinctrl properties in DT

* tag 'renesas-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas

: (26 commits)
  ARM: dts: sh73a0: Remove unnecessary clock-output-names properties
  ARM: dts: r8a73a4: Remove unnecessary clock-output-names properties
  ARM: dts: lager: Remove unnecessary clock-output-names properties
  ARM: dts: porter: Remove unnecessary clock-output-names properties
  ARM: dts: koelsch: Remove unnecessary clock-output-names properties
  ARM: dts: gose: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7794: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7793: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7791: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7779: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7778: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7740: Remove unnecessary clock-output-names properties
  ARM: dts: r7s72100: Remove unnecessary clock-output-names properties
  ARM: dts: r8a7790: Remove unnecessary clock-output-names properties
  ARM: dts: kzm9d: use generic pinctrl properties
  ARM: dts: kzm9g: use generic pinctrl properties
  ARM: dts: silk: use generic pinctrl properties
  ARM: dts: alt: use generic pinctrl properties
  ARM: dts: gose: use generic pinctrl properties
  ARM: dts: porter: use generic pinctrl properties
  ...

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents e43b7bef 000025cf

arch/arm/boot/dts/emev2-kzm9d.dts

+2 −2
Original line number Diff line number Diff line
@@ -105,8 +105,8 @@ 


&pfc {

	uart1_pins: serial@e1030000 {

		renesas,groups = "uart1_ctrl", "uart1_data";

		renesas,function = "uart1";

		groups = "uart1_ctrl", "uart1_data";

		function = "uart1";

	};

};

arch/arm/boot/dts/r7s72100.dtsi

+5 −10
Original line number Diff line number Diff line
@@ -37,46 +37,41 @@ 
		#size-cells = <1>;



		/* External clocks */

		extal_clk: extal_clk {

		extal_clk: extal {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			/* If clk present, value must be set by board */

			clock-frequency = <0>;

			clock-output-names = "extal";

		};



		usb_x1_clk: usb_x1_clk {

		usb_x1_clk: usb_x1 {

			#clock-cells = <0>;

			compatible = "fixed-clock";

			/* If clk present, value must be set by board */

			clock-frequency = <0>;

			clock-output-names = "usb_x1";

		};



		/* Fixed factor clocks */

		b_clk: b_clk {

		b_clk: b {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R7S72100_CLK_PLL>;

			clock-mult = <1>;

			clock-div = <3>;

			clock-output-names = "b";

		};

		p1_clk: p1_clk {

		p1_clk: p1 {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R7S72100_CLK_PLL>;

			clock-mult = <1>;

			clock-div = <6>;

			clock-output-names = "p1";

		};

		p0_clk: p0_clk {

		p0_clk: p0 {

			#clock-cells = <0>;

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R7S72100_CLK_PLL>;

			clock-mult = <1>;

			clock-div = <12>;

			clock-output-names = "p0";

		};



		/* Special CPG clocks */

arch/arm/boot/dts/r8a73a4-ape6evm.dts

+10 −10
Original line number Diff line number Diff line
@@ -189,28 +189,28 @@ 


&pfc {

	scifa0_pins: serial0 {

		renesas,groups = "scifa0_data";

		renesas,function = "scifa0";

		groups = "scifa0_data";

		function = "scifa0";

	};



	mmc0_pins: mmc {

		renesas,groups = "mmc0_data8", "mmc0_ctrl";

		renesas,function = "mmc0";

		groups = "mmc0_data8", "mmc0_ctrl";

		function = "mmc0";

	};



	sdhi0_pins: sd0 {

		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";

		renesas,function = "sdhi0";

		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd";

		function = "sdhi0";

	};



	sdhi1_pins: sd1 {

		renesas,groups = "sdhi1_data4", "sdhi1_ctrl";

		renesas,function = "sdhi1";

		groups = "sdhi1_data4", "sdhi1_ctrl";

		function = "sdhi1";

	};



	keyboard_pins: keyboard {

		renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327",

			       "PORT328", "PORT329";

		pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328",

		       "PORT329";

		bias-pull-up;

	};

};

arch/arm/boot/dts/r8a73a4.dtsi

+25 −50
Original line number Diff line number Diff line
@@ -486,37 +486,32 @@ 
		ranges;



		/* External root clocks */

		extalr_clk: extalr_clk {

		extalr_clk: extalr {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <32768>;

			clock-output-names = "extalr";

		};

		extal1_clk: extal1_clk {

		extal1_clk: extal1 {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <25000000>;

			clock-output-names = "extal1";

		};

		extal2_clk: extal2_clk {

		extal2_clk: extal2 {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			clock-frequency = <48000000>;

			clock-output-names = "extal2";

		};

		fsiack_clk: fsiack_clk {

		fsiack_clk: fsiack {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			/* This value must be overridden by the board. */

			clock-frequency = <0>;

			clock-output-names = "fsiack";

		};

		fsibck_clk: fsibck_clk {

		fsibck_clk: fsibck {

			compatible = "fixed-clock";

			#clock-cells = <0>;

			/* This value must be overridden by the board. */

			clock-frequency = <0>;

			clock-output-names = "fsibck";

		};



		/* Special CPG clocks */
@@ -540,171 +535,151 @@ 
			#clock-cells = <0>;

			clock-output-names = "zb";

		};

		sdhi0_clk: sdhi0_clk@e6150074 {

		sdhi0_clk: sdhi0ck@e6150074 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150074 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <0>, <&extal2_clk>;

			#clock-cells = <0>;

			clock-output-names = "sdhi0ck";

		};

		sdhi1_clk: sdhi1_clk@e6150078 {

		sdhi1_clk: sdhi1ck@e6150078 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150078 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <0>, <&extal2_clk>;

			#clock-cells = <0>;

			clock-output-names = "sdhi1ck";

		};

		sdhi2_clk: sdhi2_clk@e615007c {

		sdhi2_clk: sdhi2ck@e615007c {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe615007c 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <0>, <&extal2_clk>;

			#clock-cells = <0>;

			clock-output-names = "sdhi2ck";

		};

		mmc0_clk: mmc0_clk@e6150240 {

		mmc0_clk: mmc0@e6150240 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150240 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <0>, <&extal2_clk>;

			#clock-cells = <0>;

			clock-output-names = "mmc0";

		};

		mmc1_clk: mmc1_clk@e6150244 {

		mmc1_clk: mmc1@e6150244 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150244 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <0>, <&extal2_clk>;

			#clock-cells = <0>;

			clock-output-names = "mmc1";

		};

		vclk1_clk: vclk1_clk@e6150008 {

		vclk1_clk: vclk1@e6150008 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150008 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <0>, <&extal2_clk>, <&main_div2_clk>,

				 <&extalr_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "vclk1";

		};

		vclk2_clk: vclk2_clk@e615000c {

		vclk2_clk: vclk2@e615000c {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe615000c 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <0>, <&extal2_clk>, <&main_div2_clk>,

				 <&extalr_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "vclk2";

		};

		vclk3_clk: vclk3_clk@e615001c {

		vclk3_clk: vclk3@e615001c {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe615001c 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <0>, <&extal2_clk>, <&main_div2_clk>,

				 <&extalr_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "vclk3";

		};

		vclk4_clk: vclk4_clk@e6150014 {

		vclk4_clk: vclk4@e6150014 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150014 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <0>, <&extal2_clk>, <&main_div2_clk>,

				 <&extalr_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "vclk4";

		};

		vclk5_clk: vclk5_clk@e6150034 {

		vclk5_clk: vclk5@e6150034 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150034 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <0>, <&extal2_clk>, <&main_div2_clk>,

				 <&extalr_clk>, <0>, <0>;

			#clock-cells = <0>;

			clock-output-names = "vclk5";

		};

		fsia_clk: fsia_clk@e6150018 {

		fsia_clk: fsia@e6150018 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150018 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <&fsiack_clk>, <0>;

			#clock-cells = <0>;

			clock-output-names = "fsia";

		};

		fsib_clk: fsib_clk@e6150090 {

		fsib_clk: fsib@e6150090 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150090 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <&fsibck_clk>, <0>;

			#clock-cells = <0>;

			clock-output-names = "fsib";

		};

		mp_clk: mp_clk@e6150080 {

		mp_clk: mp@e6150080 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150080 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <&extal2_clk>, <&extal2_clk>;

			#clock-cells = <0>;

			clock-output-names = "mp";

		};

		m4_clk: m4_clk@e6150098 {

		m4_clk: m4@e6150098 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150098 0 4>;

			clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;

			#clock-cells = <0>;

			clock-output-names = "m4";

		};

		hsi_clk: hsi_clk@e615026c {

		hsi_clk: hsi@e615026c {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe615026c 0 4>;

			clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,

				 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;

			#clock-cells = <0>;

			clock-output-names = "hsi";

		};

		spuv_clk: spuv_clk@e6150094 {

		spuv_clk: spuv@e6150094 {

			compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

			reg = <0 0xe6150094 0 4>;

			clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,

				 <&extal2_clk>, <&extal2_clk>;

			#clock-cells = <0>;

			clock-output-names = "spuv";

		};



		/* Fixed factor clocks */

		main_div2_clk: main_div2_clk {

		main_div2_clk: main_div2 {

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;

			#clock-cells = <0>;

			clock-div = <2>;

			clock-mult = <1>;

			clock-output-names = "main_div2";

		};

		pll0_div2_clk: pll0_div2_clk {

		pll0_div2_clk: pll0_div2 {

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;

			#clock-cells = <0>;

			clock-div = <2>;

			clock-mult = <1>;

			clock-output-names = "pll0_div2";

		};

		pll1_div2_clk: pll1_div2_clk {

		pll1_div2_clk: pll1_div2 {

			compatible = "fixed-factor-clock";

			clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;

			#clock-cells = <0>;

			clock-div = <2>;

			clock-mult = <1>;

			clock-output-names = "pll1_div2";

		};

		extal1_div2_clk: extal1_div2_clk {

		extal1_div2_clk: extal1_div2 {

			compatible = "fixed-factor-clock";

			clocks = <&extal1_clk>;

			#clock-cells = <0>;

			clock-div = <2>;

			clock-mult = <1>;

			clock-output-names = "extal1_div2";

		};



		/* Gate clocks */

arch/arm/boot/dts/r8a7740-armadillo800eva.dts

+17 −17
Original line number Diff line number Diff line
@@ -228,44 +228,44 @@ 
	pinctrl-names = "default";



	ether_pins: ether {

		renesas,groups = "gether_mii", "gether_int";

		renesas,function = "gether";

		groups = "gether_mii", "gether_int";

		function = "gether";

	};



	scifa1_pins: serial1 {

		renesas,groups = "scifa1_data";

		renesas,function = "scifa1";

		groups = "scifa1_data";

		function = "scifa1";

	};



	st1232_pins: touchscreen {

		renesas,groups = "intc_irq10";

		renesas,function = "intc";

		groups = "intc_irq10";

		function = "intc";

	};



	backlight_pins: backlight {

		renesas,groups = "tpu0_to2_1";

		renesas,function = "tpu0";

		groups = "tpu0_to2_1";

		function = "tpu0";

	};



	mmc0_pins: mmc0 {

		renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1";

		renesas,function = "mmc0";

		groups = "mmc0_data8_1", "mmc0_ctrl_1";

		function = "mmc0";

	};



	sdhi0_pins: sd0 {

		renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";

		renesas,function = "sdhi0";

		groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp";

		function = "sdhi0";

	};



	fsia_pins: sounda {

		renesas,groups = "fsia_sclk_in", "fsia_mclk_out",

		groups = "fsia_sclk_in", "fsia_mclk_out",

			 "fsia_data_in_1", "fsia_data_out_0";

		renesas,function = "fsia";

		function = "fsia";

	};



	lcd0_pins: lcd0 {

		renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";

		renesas,function = "lcd0";

		groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync";

		function = "lcd0";



		/* DBGMD/LCDC0/FSIA MUX */

		gpio-hog;