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Commit 16613f98 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: bengal: Add support for clock drivers"

parents 78e65ac9 c7683284

arch/arm64/configs/vendor/bengal-perf_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -406,8 +406,10 @@ CONFIG_RMNET_IPA3=y 
CONFIG_RNDIS_IPA=y

CONFIG_IPA_UT=y

CONFIG_QCOM_GENI_SE=y

CONFIG_QCOM_CLK_SMD_RPM=y

CONFIG_SM_GPUCC_BENGAL=y

CONFIG_SM_DISPCC_BENGAL=y

CONFIG_SM_DEBUGCC_BENGAL=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

CONFIG_MAILBOX=y

arch/arm64/configs/vendor/bengal_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -424,6 +424,7 @@ CONFIG_RMNET_IPA3=y 
CONFIG_RNDIS_IPA=y

CONFIG_IPA_UT=y

CONFIG_QCOM_GENI_SE=y

CONFIG_QCOM_CLK_SMD_RPM=y

CONFIG_SM_GPUCC_BENGAL=y

CONFIG_SM_DISPCC_BENGAL=y

CONFIG_SM_DEBUGCC_BENGAL=y

drivers/clk/qcom/clk-smd-rpm.c

+487 −204

File changed.

Preview size limit exceeded, changes collapsed.

include/dt-bindings/clock/qcom,rpmcc.h

+107 −99
Original line number Diff line number Diff line
@@ -109,8 +109,10 @@ 
#define RPM_SMD_DIV_A_CLK1			59

#define RPM_SMD_DIV_CLK2			60

#define RPM_SMD_DIV_A_CLK2			61

#define RPM_SMD_DIFF_CLK			62

#define RPM_SMD_DIFF_A_CLK			63

#define RPM_SMD_DIV_CLK3			61

#define RPM_SMD_DIV_A_CLK3			62

#define RPM_SMD_DIFF_CLK			63

#define RPM_SMD_DIFF_A_CLK			64

#define RPM_SMD_CXO_D0_PIN			64

#define RPM_SMD_CXO_D0_A_PIN			65

#define RPM_SMD_CXO_D1_PIN			66
@@ -141,66 +143,72 @@ 
#define RPM_SMD_LN_BB_CLK2_A			91

#define RPM_SMD_LN_BB_CLK3			92

#define RPM_SMD_LN_BB_CLK3_A			93

#define PNOC_MSMBUS_CLK				94

#define PNOC_MSMBUS_A_CLK			95

#define PNOC_KEEPALIVE_A_CLK			96

#define SNOC_MSMBUS_CLK				97

#define SNOC_MSMBUS_A_CLK			98

#define BIMC_MSMBUS_CLK				99

#define BIMC_MSMBUS_A_CLK			100

#define PNOC_USB_CLK				101

#define PNOC_USB_A_CLK				102

#define SNOC_USB_CLK				103

#define SNOC_USB_A_CLK				104

#define BIMC_USB_CLK				105

#define BIMC_USB_A_CLK				106

#define SNOC_WCNSS_A_CLK			107

#define BIMC_WCNSS_A_CLK			108

#define MCD_CE1_CLK				109

#define QCEDEV_CE1_CLK				110

#define QCRYPTO_CE1_CLK				111

#define QSEECOM_CE1_CLK				112

#define SCM_CE1_CLK				113

#define CXO_SMD_OTG_CLK				114

#define CXO_SMD_LPM_CLK				115

#define CXO_SMD_PIL_PRONTO_CLK			116

#define CXO_SMD_PIL_MSS_CLK			117

#define CXO_SMD_WLAN_CLK			118

#define CXO_SMD_PIL_LPASS_CLK			119

#define CXO_SMD_PIL_CDSP_CLK			120

#define CNOC_MSMBUS_CLK				121

#define CNOC_MSMBUS_A_CLK				122

#define CNOC_KEEPALIVE_A_CLK				123

#define SNOC_KEEPALIVE_A_CLK				124

#define CPP_MMNRT_MSMBUS_CLK				125

#define CPP_MMNRT_MSMBUS_A_CLK				126

#define JPEG_MMNRT_MSMBUS_CLK				127

#define JPEG_MMNRT_MSMBUS_A_CLK				128

#define VENUS_MMNRT_MSMBUS_CLK				129

#define VENUS_MMNRT_MSMBUS_A_CLK			130

#define ARM9_MMNRT_MSMBUS_CLK				131

#define ARM9_MMNRT_MSMBUS_A_CLK				132

#define MDP_MMRT_MSMBUS_CLK				133

#define MDP_MMRT_MSMBUS_A_CLK				134

#define VFE_MMRT_MSMBUS_CLK				135

#define VFE_MMRT_MSMBUS_A_CLK				136

#define QUP0_MSMBUS_SNOC_PERIPH_CLK			137

#define QUP0_MSMBUS_SNOC_PERIPH_A_CLK			138

#define QUP1_MSMBUS_SNOC_PERIPH_CLK			139

#define QUP1_MSMBUS_SNOC_PERIPH_A_CLK			140

#define QUP2_MSMBUS_SNOC_PERIPH_CLK                     141

#define QUP2_MSMBUS_SNOC_PERIPH_A_CLK                   142

#define DAP_MSMBUS_SNOC_PERIPH_CLK			143

#define DAP_MSMBUS_SNOC_PERIPH_A_CLK			144

#define SDC1_MSMBUS_SNOC_PERIPH_CLK			145

#define SDC1_MSMBUS_SNOC_PERIPH_A_CLK			146

#define SDC2_MSMBUS_SNOC_PERIPH_CLK			147

#define SDC2_MSMBUS_SNOC_PERIPH_A_CLK			148

#define CRYPTO_MSMBUS_SNOC_PERIPH_CLK			149

#define CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK			150

#define SDC1_SLV_MSMBUS_SNOC_PERIPH_CLK			151

#define SDC1_SLV_MSMBUS_SNOC_PERIPH_A_CLK		152

#define SDC2_SLV_MSMBUS_SNOC_PERIPH_CLK			153

#define SDC2_SLV_MSMBUS_SNOC_PERIPH_A_CLK		154

#define RPM_SMD_MMAXI_CLK			94

#define RPM_SMD_MMAXI_A_CLK			95

#define RPM_SMD_AGGR1_NOC_CLK			96

#define RPM_SMD_AGGR1_NOC_A_CLK			97

#define RPM_SMD_AGGR2_NOC_CLK			98

#define RPM_SMD_AGGR2_NOC_A_CLK			99

#define PNOC_MSMBUS_CLK				100

#define PNOC_MSMBUS_A_CLK			101

#define PNOC_KEEPALIVE_A_CLK			102

#define SNOC_MSMBUS_CLK				103

#define SNOC_MSMBUS_A_CLK			104

#define BIMC_MSMBUS_CLK				105

#define BIMC_MSMBUS_A_CLK			106

#define PNOC_USB_CLK				107

#define PNOC_USB_A_CLK				108

#define SNOC_USB_CLK				109

#define SNOC_USB_A_CLK				110

#define BIMC_USB_CLK				111

#define BIMC_USB_A_CLK				112

#define SNOC_WCNSS_A_CLK			113

#define BIMC_WCNSS_A_CLK			114

#define MCD_CE1_CLK				115

#define QCEDEV_CE1_CLK				116

#define QCRYPTO_CE1_CLK				117

#define QSEECOM_CE1_CLK				118

#define SCM_CE1_CLK				119

#define CXO_SMD_OTG_CLK				120

#define CXO_SMD_LPM_CLK				121

#define CXO_SMD_PIL_PRONTO_CLK			122

#define CXO_SMD_PIL_MSS_CLK			123

#define CXO_SMD_WLAN_CLK			124

#define CXO_SMD_PIL_LPASS_CLK			125

#define CXO_SMD_PIL_CDSP_CLK			126

#define CNOC_MSMBUS_CLK				127

#define CNOC_MSMBUS_A_CLK			128

#define CNOC_KEEPALIVE_A_CLK			129

#define SNOC_KEEPALIVE_A_CLK			130

#define CPP_MMNRT_MSMBUS_CLK			131

#define CPP_MMNRT_MSMBUS_A_CLK			132

#define JPEG_MMNRT_MSMBUS_CLK			133

#define JPEG_MMNRT_MSMBUS_A_CLK			134

#define VENUS_MMNRT_MSMBUS_CLK			135

#define VENUS_MMNRT_MSMBUS_A_CLK		136

#define ARM9_MMNRT_MSMBUS_CLK			137

#define ARM9_MMNRT_MSMBUS_A_CLK			138

#define MDP_MMRT_MSMBUS_CLK			139

#define MDP_MMRT_MSMBUS_A_CLK			140

#define VFE_MMRT_MSMBUS_CLK			141

#define VFE_MMRT_MSMBUS_A_CLK			142

#define QUP0_MSMBUS_SNOC_PERIPH_CLK		143

#define QUP0_MSMBUS_SNOC_PERIPH_A_CLK		144

#define QUP1_MSMBUS_SNOC_PERIPH_CLK		145

#define QUP1_MSMBUS_SNOC_PERIPH_A_CLK		146

#define QUP2_MSMBUS_SNOC_PERIPH_CLK             147

#define QUP2_MSMBUS_SNOC_PERIPH_A_CLK           148

#define DAP_MSMBUS_SNOC_PERIPH_CLK		149

#define DAP_MSMBUS_SNOC_PERIPH_A_CLK		150

#define SDC1_MSMBUS_SNOC_PERIPH_CLK		151

#define SDC1_MSMBUS_SNOC_PERIPH_A_CLK		152

#define SDC2_MSMBUS_SNOC_PERIPH_CLK		153

#define SDC2_MSMBUS_SNOC_PERIPH_A_CLK		154

#define CRYPTO_MSMBUS_SNOC_PERIPH_CLK		155

#define CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK		156

#define SDC1_SLV_MSMBUS_SNOC_PERIPH_CLK		157

#define SDC1_SLV_MSMBUS_SNOC_PERIPH_A_CLK	158

#define SDC2_SLV_MSMBUS_SNOC_PERIPH_CLK		159

#define SDC2_SLV_MSMBUS_SNOC_PERIPH_A_CLK	160



#endif

include/linux/soc/qcom/smd-rpm.h

+2 −0
Original line number Diff line number Diff line
@@ -32,6 +32,8 @@ struct qcom_smd_rpm; 
#define QCOM_SMD_RPM_IPA_CLK	0x617069

#define QCOM_SMD_RPM_CE_CLK	0x6563

#define QCOM_SMD_RPM_AGGR_CLK	0x72676761

#define QCOM_SMD_RPM_QUP_CLK    0x00707571

#define QCOM_SMD_RPM_MMXI_CLK   0x69786D6D



int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,

		       int state,