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Commit 165f6064 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'usb-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next 



Felipe writes:

usb: patches for v3.12 merge window

All patches here have been pending on linux-usb
and sitting in linux-next for a while now.

The biggest things in this tag are:

DWC3 learned proper usage of threaded IRQ
handlers and now we spend very little time
in hardirq context.

MUSB now has proper support for BeagleBone and
Beaglebone Black.

Tegra's USB support also got quite a bit of love
and is learning to use PHY layer and generic DT
attributes.

Other than that, the usual pack of cleanups and
non-critical fixes follow.

Signed-of-by: default avatarFelipe Balbi <balbi@ti.com>

Conflicts:
	drivers/usb/gadget/udc-core.c
	drivers/usb/host/ehci-tegra.c
	drivers/usb/musb/omap2430.c
	drivers/usb/musb/tusb6010.c
parents c23bda36 8b841cb2

Documentation/devicetree/bindings/usb/dwc3.txt

+5 −3
Original line number Original line Diff line number Diff line
@@ -3,10 +3,12 @@ synopsys DWC3 CORE 
DWC3- USB3 CONTROLLER

DWC3- USB3 CONTROLLER





Required properties:

Required properties:

 - compatible: must be "synopsys,dwc3"

 - compatible: must be "snps,dwc3"

 - reg : Address and length of the register set for the device

 - reg : Address and length of the register set for the device

 - interrupts: Interrupts used by the dwc3 controller.

 - interrupts: Interrupts used by the dwc3 controller.

 - usb-phy : array of phandle for the PHY device

 - usb-phy : array of phandle for the PHY device.  The first element

   in the array is expected to be a handle to the USB2/HS PHY and

   the second element is expected to be a handle to the USB3/SS PHY





Optional properties:

Optional properties:

 - tx-fifo-resize: determines if the FIFO *has* to be reallocated.

 - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
@@ -14,7 +16,7 @@ Optional properties: 
This is usually a subnode to DWC3 glue to which it is connected.

This is usually a subnode to DWC3 glue to which it is connected.





dwc3@4a030000 {

dwc3@4a030000 {

	compatible = "synopsys,dwc3";

	compatible = "snps,dwc3";

	reg = <0x4a030000 0xcfff>;

	reg = <0x4a030000 0xcfff>;

	interrupts = <0 92 4>

	interrupts = <0 92 4>

	usb-phy = <&usb2_phy>, <&usb3,phy>;

	usb-phy = <&usb2_phy>, <&usb3,phy>;

Documentation/devicetree/bindings/usb/generic.txt

0 → 100644
+24 −0
Original line number Original line Diff line number Diff line 
Generic USB Properties



Optional properties:

 - maximum-speed: tells USB controllers we want to work up to a certain

			speed. Valid arguments are "super-speed", "high-speed",

			"full-speed" and "low-speed". In case this isn't passed

			via DT, USB controllers should default to their maximum

			HW capability.

 - dr_mode: tells Dual-Role USB controllers that we want to work on a

			particular mode. Valid arguments are "host",

			"peripheral" and "otg". In case this attribute isn't

			passed via DT, USB DRD controllers should default to

			OTG.



This is an attribute to a USB controller such as:



dwc3@4a030000 {

	compatible = "synopsys,dwc3";

	reg = <0x4a030000 0xcfff>;

	interrupts = <0 92 4>

	usb-phy = <&usb2_phy>, <&usb3,phy>;

	maximum-speed = "super-speed";

	dr_mode = "otg";

};

Documentation/devicetree/bindings/usb/nvidia,tegra20-usb-phy.txt

+13 −4
Original line number Original line Diff line number Diff line
@@ -3,7 +3,7 @@ Tegra SOC USB PHY 
The device node for Tegra SOC USB PHY:

The device node for Tegra SOC USB PHY:





Required properties :

Required properties :

 - compatible : Should be "nvidia,tegra20-usb-phy".

 - compatible : Should be "nvidia,tegra<chip>-usb-phy".

 - reg : Defines the following set of registers, in the order listed:

 - reg : Defines the following set of registers, in the order listed:

   - The PHY's own register set.

   - The PHY's own register set.

     Always present.

     Always present.
@@ -24,17 +24,26 @@ Required properties : 
Required properties for phy_type == ulpi:

Required properties for phy_type == ulpi:

  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.

  - nvidia,phy-reset-gpio : The GPIO used to reset the PHY.





Required PHY timing params for utmi phy:

Required PHY timing params for utmi phy, for all chips:

  - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before

  - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before

    start of sync launches RxActive

    start of sync launches RxActive

  - nvidia,elastic-limit : Variable FIFO Depth of elastic input store

  - nvidia,elastic-limit : Variable FIFO Depth of elastic input store

  - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait

  - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait

    before declare IDLE.

    before declare IDLE.

  - nvidia,term-range-adj : Range adjusment on terminations

  - nvidia,term-range-adj : Range adjusment on terminations

  - nvidia,xcvr-setup : HS driver output control

  - Either one of the following for HS driver output control:

    - nvidia,xcvr-setup : integer, uses the provided value.

    - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read

      from the on-chip fuses

    If both are provided, nvidia,xcvr-setup-use-fuses takes precedence.

  - nvidia,xcvr-lsfslew : LS falling slew rate control.

  - nvidia,xcvr-lsfslew : LS falling slew rate control.

  - nvidia,xcvr-lsrslew :  LS rising slew rate control.

  - nvidia,xcvr-lsrslew :  LS rising slew rate control.





Required PHY timing params for utmi phy, only on Tegra30 and above:

  - nvidia,xcvr-hsslew : HS slew rate control.

  - nvidia,hssquelch-level : HS squelch detector level.

  - nvidia,hsdiscon-level : HS disconnect detector level.



Optional properties:

Optional properties:

  - nvidia,has-legacy-mode : boolean indicates whether this controller can

  - nvidia,has-legacy-mode : boolean indicates whether this controller can

    operate in legacy mode (as APX 2500 / 2600). In legacy mode some

    operate in legacy mode (as APX 2500 / 2600). In legacy mode some
@@ -48,5 +57,5 @@ Optional properties: 
      peripheral means it is device controller

      peripheral means it is device controller

      otg means it can operate as either ("on the go")

      otg means it can operate as either ("on the go")





Required properties for dr_mode == otg:

VBUS control (required for dr_mode == otg, optional for dr_mode == host):

  - vbus-supply: regulator for VBUS
 
  - vbus-supply: regulator for VBUS

Documentation/devicetree/bindings/usb/samsung-hsotg.txt

0 → 100644
+40 −0
Original line number Original line Diff line number Diff line 
Samsung High Speed USB OTG controller

-----------------------------



The Samsung HSOTG IP can be found on Samsung SoCs, from S3C6400 onwards.

It gives functionality of OTG-compliant USB 2.0 host and device with

support for USB 2.0 high-speed (480Mbps) and full-speed (12 Mbps)

operation.



Currently only device mode is supported.



Binding details

-----



Required properties:

- compatible: "samsung,s3c6400-hsotg" should be used for all currently

    supported SoC,

- interrupt-parent: phandle for the interrupt controller to which the

    interrupt signal of the HSOTG block is routed,

- interrupts: specifier of interrupt signal of interrupt controller,

    according to bindings of interrupt controller,

- clocks: contains an array of clock specifiers:

    - first entry: OTG clock

- clock-names: contains array of clock names:

    - first entry: must be "otg"

- vusb_d-supply: phandle to voltage regulator of digital section,

- vusb_a-supply: phandle to voltage regulator of analog section.



Example

-----



	hsotg@12480000 {

		compatible = "samsung,s3c6400-hsotg";

		reg = <0x12480000 0x20000>;

		interrupts = <0 71 0>;

		clocks = <&clock 305>;

		clock-names = "otg";

		vusb_d-supply = <&vusb_reg>;

		vusb_a-supply = <&vusbdac_reg>;

	};

arch/arm/boot/dts/am335x-bone.dts

+16 −0
Original line number Original line Diff line number Diff line
@@ -120,6 +120,22 @@ 
			status = "okay";

			status = "okay";

		};

		};





		musb: usb@47400000 {

			status = "okay";



			control@44e10000 {

				status = "okay";

			};



			phy@47401300 {

				status = "okay";

			};



			usb@47401000 {

				status = "okay";

			};

		};



		i2c0: i2c@44e0b000 {

		i2c0: i2c@44e0b000 {

			pinctrl-names = "default";

			pinctrl-names = "default";

			pinctrl-0 = <&i2c0_pins>;

			pinctrl-0 = <&i2c0_pins>;