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Commit 162b20d2 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux into drm-next 

A few more patches for 4.8.  Mostly bug fixes and some prep work
for iceland powerplay support.  I have a couple polaris patches and
Edward's misc cleanups that require a merge with Linus'.  I don't know
if you are planning a merge anytime soon.

[airlied: fixed up endian vs 32-bit change in ppatomctrl]

* 'drm-next-4.8' of git://people.freedesktop.org/~agd5f/linux: (26 commits)
  drm/amdgpu: comment out unused defaults_bonaire_pro static const structures to fix the build
  drm/amdgpu: temporary comment out unused static const structures to fix the build
  drm/amdgpu: S3 resume fail on Polaris10
  drm/amd/powerplay: add pp_tables_get_response_times function in process pptables
  drm/amd/powerplay: fix the incorrect return value
  drm/amd/powerplay: add atomctrl_get_voltage_evv function in ppatomctrl
  drm/amdgpu: add new definitions into ppsmc.h for iceland
  drm/amd/powerplay: add SMU register macro for future use
  drm/amdgpu: add ucode_start_address into cgs_firmware_info
  drm/amdgpu: no need load microcode at sdma if powerplay is enabled
  drm/amdgpu: rename smumgr to smum for dpm
  drm/amdgpu: disable GFX PG on CZ/BR/ST
  drivers: gpu: drm: amd: powerplay: hwmgr: Remove unused variable
  drm/amdgpu: return -ENOSPC when running out of UVD handles
  drm/amdgpu: trace need_flush in grab_vm as well
  drm/amdgpu: always signal all fences
  drm/amdgpu: check flush fence context instead of same ring v2
  drm/radeon: support backlight control for UNIPHY3
  drm/amdgpu: support backlight control for UNIPHY3
  drm/amdgpu: remove usec timeout loop from IB tests
  ...
parents c3f8d864 5ef82929

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+4 −0
Original line number Diff line number Diff line
@@ -752,6 +752,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, 


		if (!adev->pm.fw) {

			switch (adev->asic_type) {

			case CHIP_TOPAZ:

				strcpy(fw_name, "amdgpu/topaz_smc.bin");

				break;

			case CHIP_TONGA:

				strcpy(fw_name, "amdgpu/tonga_smc.bin");

				break;
@@ -800,6 +803,7 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, 


		info->version = adev->pm.fw_version;

		info->image_size = ucode_size;

		info->ucode_start_address = ucode_start_address;

		info->kptr = (void *)src;

	}

	return 0;

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+13 −4
Original line number Diff line number Diff line
@@ -204,16 +204,25 @@ void amdgpu_fence_process(struct amdgpu_ring *ring) 
	if (seq != ring->fence_drv.sync_seq)

		amdgpu_fence_schedule_fallback(ring);



	while (last_seq != seq) {

	if (unlikely(seq == last_seq))

		return;



	last_seq &= drv->num_fences_mask;

	seq &= drv->num_fences_mask;



	do {

		struct fence *fence, **ptr;



		ptr = &drv->fences[++last_seq & drv->num_fences_mask];

		++last_seq;

		last_seq &= drv->num_fences_mask;

		ptr = &drv->fences[last_seq];



		/* There is always exactly one thread signaling this fence slot */

		fence = rcu_dereference_protected(*ptr, 1);

		RCU_INIT_POINTER(*ptr, NULL);



		BUG_ON(!fence);

		if (!fence)

			continue;



		r = fence_signal(fence);

		if (!r)
@@ -222,7 +231,7 @@ void amdgpu_fence_process(struct amdgpu_ring *ring) 
			BUG();



		fence_put(fence);

	}

	} while (last_seq != seq);

}



/**

drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

+1 −5
Original line number Diff line number Diff line
@@ -122,7 +122,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	bool skip_preamble, need_ctx_switch;

	unsigned patch_offset = ~0;

	struct amdgpu_vm *vm;

	struct fence *hwf;

	uint64_t ctx;



	unsigned i;
@@ -190,7 +189,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
	if (ring->funcs->emit_hdp_invalidate)

		amdgpu_ring_emit_hdp_invalidate(ring);



	r = amdgpu_fence_emit(ring, &hwf);

	r = amdgpu_fence_emit(ring, f);

	if (r) {

		dev_err(adev->dev, "failed to emit fence (%d)\n", r);

		if (job && job->vm_id)
@@ -205,9 +204,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 
				       AMDGPU_FENCE_FLAG_64BIT);

	}



	if (f)

		*f = fence_get(hwf);



	if (patch_offset != ~0 && ring->funcs->patch_cond_exec)

		amdgpu_ring_patch_cond_exec(ring, patch_offset);

drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

+3 −5
Original line number Diff line number Diff line
@@ -172,15 +172,13 @@ static struct fence *amdgpu_job_run(struct amd_sched_job *sched_job) 
	trace_amdgpu_sched_run_job(job);

	r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,

			       job->sync.last_vm_update, job, &fence);

	if (r) {

	if (r)

		DRM_ERROR("Error scheduling IBs (%d)\n", r);

		goto err;

	}



err:

	/* if gpu reset, hw fence will be replaced here */

	fence_put(job->fence);

	job->fence = fence;

	job->fence = fence_get(fence);

	amdgpu_job_free_resources(job);

	return fence;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h

+9 −7
Original line number Diff line number Diff line
@@ -149,24 +149,26 @@ TRACE_EVENT(amdgpu_sched_run_job, 




TRACE_EVENT(amdgpu_vm_grab_id,

	    TP_PROTO(struct amdgpu_vm *vm, int ring, unsigned vmid,

		     uint64_t pd_addr),

	    TP_ARGS(vm, ring, vmid, pd_addr),

	    TP_PROTO(struct amdgpu_vm *vm, int ring, struct amdgpu_job *job),

	    TP_ARGS(vm, ring, job),

	    TP_STRUCT__entry(

			     __field(struct amdgpu_vm *, vm)

			     __field(u32, ring)

			     __field(u32, vmid)

			     __field(u64, pd_addr)

			     __field(u32, needs_flush)

			     ),



	    TP_fast_assign(

			   __entry->vm = vm;

			   __entry->ring = ring;

			   __entry->vmid = vmid;

			   __entry->pd_addr = pd_addr;

			   __entry->vmid = job->vm_id;

			   __entry->pd_addr = job->vm_pd_addr;

			   __entry->needs_flush = job->vm_needs_flush;

			   ),

	    TP_printk("vm=%p, ring=%u, id=%u, pd_addr=%010Lx", __entry->vm,

		      __entry->ring, __entry->vmid, __entry->pd_addr)

	    TP_printk("vm=%p, ring=%u, id=%u, pd_addr=%010Lx needs_flush=%u",

		      __entry->vm, __entry->ring, __entry->vmid,

		      __entry->pd_addr, __entry->needs_flush)

);



TRACE_EVENT(amdgpu_vm_bo_map,