Loading arch/arm64/boot/dts/qcom/kona.dtsi +17 −3 Original line number Diff line number Diff line Loading @@ -586,6 +586,15 @@ clock-output-names = "bi_tcxo"; }; clocks { sleep_clk: sleep-clk { compatible = "fixed-clock"; clock-frequency = <32000>; clock-output-names = "chip_sleep_clk"; #clock-cells = <1>; }; }; clock_rpmh: qcom,rpmhclk { compatible = "qcom,dummycc"; clock-output-names = "rpmh_clocks"; Loading Loading @@ -616,9 +625,14 @@ #reset-cells = <1>; }; clock_videocc: qcom,videocc { compatible = "qcom,dummycc"; clock-output-names = "videocc_clocks"; clock_videocc: qcom,videocc@abf0000 { compatible = "qcom,videocc-kona", "syscon"; reg = <0xabf0000 0x10000>; reg-names = "cc_base"; vdd_mx-supply = <&VDD_MX_LEVEL>; vdd_mm-supply = <&VDD_MMCX_LEVEL>; clock-names = "cfg_ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; #clock-cells = <1>; #reset-cells = <1>; }; Loading Loading
arch/arm64/boot/dts/qcom/kona.dtsi +17 −3 Original line number Diff line number Diff line Loading @@ -586,6 +586,15 @@ clock-output-names = "bi_tcxo"; }; clocks { sleep_clk: sleep-clk { compatible = "fixed-clock"; clock-frequency = <32000>; clock-output-names = "chip_sleep_clk"; #clock-cells = <1>; }; }; clock_rpmh: qcom,rpmhclk { compatible = "qcom,dummycc"; clock-output-names = "rpmh_clocks"; Loading Loading @@ -616,9 +625,14 @@ #reset-cells = <1>; }; clock_videocc: qcom,videocc { compatible = "qcom,dummycc"; clock-output-names = "videocc_clocks"; clock_videocc: qcom,videocc@abf0000 { compatible = "qcom,videocc-kona", "syscon"; reg = <0xabf0000 0x10000>; reg-names = "cc_base"; vdd_mx-supply = <&VDD_MX_LEVEL>; vdd_mm-supply = <&VDD_MMCX_LEVEL>; clock-names = "cfg_ahb_clk"; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; #clock-cells = <1>; #reset-cells = <1>; }; Loading