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Commit 161ec53c authored by Fenghua Yu's avatar Fenghua Yu Committed by H. Peter Anvin
Browse files

x86, mem, intel: Initialize Enhanced REP MOVSB/STOSB 



If kernel intends to use enhanced REP MOVSB/STOSB, it must ensure
IA32_MISC_ENABLE.Fast_String_Enable (bit 0) is set and CPUID.(EAX=07H, ECX=0H):
EBX[bit 9] also reports 1.

Signed-off-by: default avatarFenghua Yu <fenghua.yu@intel.com>
Link: http://lkml.kernel.org/r/1305671358-14478-3-git-send-email-fenghua.yu@intel.com


Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent 724a92ee

arch/x86/kernel/cpu/intel.c

+15 −4
Original line number Diff line number Diff line
@@ -29,10 +29,10 @@ 


static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)

{

	/* Unmask CPUID levels if masked: */

	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {

	u64 misc_enable;



	/* Unmask CPUID levels if masked: */

	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {

		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);



		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
@@ -118,8 +118,6 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 
	 * (model 2) with the same problem.

	 */

	if (c->x86 == 15) {

		u64 misc_enable;



		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);



		if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
@@ -130,6 +128,19 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 
		}

	}

#endif



	/*

	 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,

	 * clear the fast string and enhanced fast string CPU capabilities.

	 */

	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {

		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);

		if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {

			printk(KERN_INFO "Disabled fast string operations\n");

			setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);

			setup_clear_cpu_cap(X86_FEATURE_ERMS);

		}

	}

}



#ifdef CONFIG_X86_32