Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 15005a32 authored by Don Skidmore's avatar Don Skidmore Committed by David S. Miller
Browse files

ixgbe: fix dca issue with relaxed ordering turned on 



The is an issue where setting Relaxed Ordering (RO) bit
(in a PCI-E write transaction) on 82598 causing the chipset
to drop DCA hints.  This patch forces RO not to be set for
descriptors as well as payload.  This will only be in effect
while DCA is enabled and no performance difference was
noticed in testing.

Signed-off-by: default avatarDon Skidmore <donald.c.skidmore@intel.com>
Signed-off-by: default avatarPeter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 67fd1a73

drivers/net/ixgbe/ixgbe_main.c

+3 −0
Original line number Diff line number Diff line
@@ -318,6 +318,9 @@ static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 
		rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);

		rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;

		rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;

		rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);

		rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |

			    IXGBE_DCA_RXCTRL_DESC_HSRO_EN);

		IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);

		rx_ring->cpu = cpu;

	}

drivers/net/ixgbe/ixgbe_type.h

+3 −0
Original line number Diff line number Diff line
@@ -404,6 +404,9 @@ 
#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */

#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */

#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */

#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */

#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */

#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */



#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */

#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */