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Commit 14f00d5e authored by Santosh Mardi's avatar Santosh Mardi
Browse files

ARM: dts: msm: update memlat nodes lito target 

memlat monitor design is changed to parent-child design, update
the memlat nodes for lito target according to the latest design.

Change-Id: I4ab8819bf2a58d17d9612917b4d9a9bb51b1978e
parent 39c17d11

qcom/lito.dtsi

+141 −131
Original line number Diff line number Diff line
@@ -2659,6 +2659,37 @@ 
		status = "disabled";

	};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;



		cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
@@ -2672,6 +2703,82 @@ 
				< 1728000 1420000000 >;

		};



		cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

			qcom,target-dev = <&cpu0_cpu_llcc_lat>;

			qcom,cachemiss-ev = <0x2A>;

			qcom,core-dev-table =

				< 1228800 MHZ_TO_MBPS(300, 16) >,

				< 1459200 MHZ_TO_MBPS(466, 16) >,

				< 1728000 MHZ_TO_MBPS(600, 16) >;

		};



		cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

			qcom,target-dev = <&cpu0_llcc_ddr_lat>;

			qcom,cachemiss-ev = <0x1000>;

			qcom,core-dev-table =

				<  672000 MHZ_TO_MBPS( 300, 4) >,

				<  940800 MHZ_TO_MBPS( 451, 4) >,

				< 1228800 MHZ_TO_MBPS( 547, 4) >,

				< 1459200 MHZ_TO_MBPS( 768, 4) >,

				< 1728000 MHZ_TO_MBPS(1017, 4) >;

		};



		cpu0_computemon: qcom,cpu0-computemon {

			compatible = "qcom,arm-compute-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

			qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;

			qcom,core-dev-table =

				<  672000 MHZ_TO_MBPS( 300, 4) >,

				< 1228800 MHZ_TO_MBPS( 451, 4) >,

				< 1459200 MHZ_TO_MBPS( 547, 4) >,

				< 1728000 MHZ_TO_MBPS( 768, 4) >;

		};

	};



	cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu7_cpu_ddr_latfloor: qcom,cpu7-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {

		compatible = "qcom,arm-memlat-cpugrp";

		qcom,cpulist = <&CPU6 &CPU7>;



		cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU6>;
@@ -2698,35 +2805,6 @@ 
				< 2323200 1420000000 >;

		};



	cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



	cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		qcom,target-dev = <&cpu0_cpu_llcc_lat>;

		qcom,cachemiss-ev = <0x2A>;

		qcom,core-dev-table =

			< 1228800 MHZ_TO_MBPS(300, 16) >,

			< 1459200 MHZ_TO_MBPS(466, 16) >,

			< 1728000 MHZ_TO_MBPS(600, 16) >;

	};



	cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;

		qcom,active-only;

		operating-points-v2 = <&llcc_bw_opp_table>;

	};



		cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU6 &CPU7>;
@@ -2741,37 +2819,6 @@ 
				< 3000000 MHZ_TO_MBPS(1066, 16) >;

		};



	cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {

		compatible = "qcom,arm-memlat-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		qcom,target-dev = <&cpu0_llcc_ddr_lat>;

		qcom,cachemiss-ev = <0x1000>;

		qcom,core-dev-table =

			<  672000 MHZ_TO_MBPS( 300, 4) >,

			<  940800 MHZ_TO_MBPS( 451, 4) >,

			< 1228800 MHZ_TO_MBPS( 547, 4) >,

			< 1459200 MHZ_TO_MBPS( 768, 4) >,

			< 1728000 MHZ_TO_MBPS(1017, 4) >;

	};



	cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



		cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon {

			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU6 &CPU7>;
@@ -2786,37 +2833,8 @@ 
				< 3000000 MHZ_TO_MBPS(2092, 4) >;

		};



	cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



	cpu0_computemon: qcom,cpu0-computemon {

		compatible = "qcom,arm-cpu-mon";

		qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;

		qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;

		qcom,core-dev-table =

			<  672000 MHZ_TO_MBPS( 300, 4) >,

			< 1228800 MHZ_TO_MBPS( 451, 4) >,

			< 1459200 MHZ_TO_MBPS( 547, 4) >,

			< 1728000 MHZ_TO_MBPS( 768, 4) >;

	};



	cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



		cpu6_computemon: qcom,cpu6-computemon {

		compatible = "qcom,arm-cpu-mon";

			compatible = "qcom,arm-compute-mon";

			qcom,cpulist = <&CPU6>;

			qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;

			qcom,core-dev-table =
@@ -2828,17 +2846,8 @@ 
				< 3000000 MHZ_TO_MBPS(2092, 4) >;

		};



	cpu7_cpu_ddr_latfloor: qcom,cpu7-cpu-ddr-latfloor {

		compatible = "qcom,devbw";

		governor = "performance";

		qcom,src-dst-ports =

			<MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;

		qcom,active-only;

		operating-points-v2 = <&ddr_bw_opp_table>;

	};



		cpu7_computemon: qcom,cpu7-computemon {

		compatible = "qcom,arm-cpu-mon";

			compatible = "qcom,arm-compute-mon";

			qcom,cpulist = <&CPU7>;

			qcom,target-dev = <&cpu7_cpu_ddr_latfloor>;

			qcom,core-dev-table =
@@ -2849,6 +2858,7 @@ 
				< 2649600 MHZ_TO_MBPS(1804, 4) >,

				< 3000000 MHZ_TO_MBPS(2092, 4) >;

		};

	};



	qcom,msm_gsi {

		compatible = "qcom,msm_gsi";