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Commit 14d8d776 authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Bjorn Helgaas
Browse files

Merge branch 'lorenzo/pci/endpoint' 

* lorenzo/pci/endpoint:
  misc: pci_endpoint_test: Handle 64-bit BARs properly
  PCI: designware-ep: Make dw_pcie_ep_reset_bar() handle 64-bit BARs properly
  PCI: endpoint: Make sure that BAR_5 does not have 64-bit flag set when clearing
  PCI: endpoint: Make epc->ops->clear_bar()/pci_epc_clear_bar() take struct *epf_bar
  PCI: endpoint: Handle 64-bit BARs properly
  PCI: cadence: Set PCI_BASE_ADDRESS_MEM_TYPE_64 if a 64-bit BAR was set-up
  PCI: designware-ep: Make dw_pcie_ep_set_bar() handle 64-bit BARs properly
  PCI: endpoint: Setting a BAR size > 4 GB is invalid if 64-bit flag is not set
  PCI: endpoint: Setting 64-bit/prefetch bit is invalid when IO is set
  PCI: endpoint: Setting BAR_5 to 64-bits wide is invalid
  PCI: endpoint: Simplify epc->ops->set_bar()/pci_epc_set_bar()
  PCI: endpoint: BAR width should not depend on sizeof dma_addr_t
  PCI: endpoint: Remove goto labels in pci_epf_create()
  PCI: endpoint: Fix kernel panic after put_device()
  PCI: endpoint: Simplify name allocation for EPF device
parents 1ad9a873 16b17cad

drivers/misc/pci_endpoint_test.c

+7 −5
Original line number Diff line number Diff line
@@ -534,6 +534,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, 
	}



	for (bar = BAR_0; bar <= BAR_5; bar++) {

		if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {

			base = pci_ioremap_bar(pdev, bar);

			if (!base) {

				dev_err(dev, "failed to read BAR%d\n", bar);
@@ -541,6 +542,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, 
			}

			test->bar[bar] = base;

		}

	}



	test->base = test->bar[test_reg_bar];

	if (!test->base) {

drivers/pci/cadence/pcie-cadence-ep.c

+11 −4
Original line number Diff line number Diff line
@@ -77,16 +77,19 @@ static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, 
	return 0;

}



static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, enum pci_barno bar,

				dma_addr_t bar_phys, size_t size, int flags)

static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,

				struct pci_epf_bar *epf_bar)

{

	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);

	struct cdns_pcie *pcie = &ep->pcie;

	dma_addr_t bar_phys = epf_bar->phys_addr;

	enum pci_barno bar = epf_bar->barno;

	int flags = epf_bar->flags;

	u32 addr0, addr1, reg, cfg, b, aperture, ctrl;

	u64 sz;



	/* BAR size is 2^(aperture + 7) */

	sz = max_t(size_t, size, CDNS_PCIE_EP_MIN_APERTURE);

	sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE);

	/*

	 * roundup_pow_of_two() returns an unsigned long, which is not suited

	 * for 64bit values.
@@ -103,6 +106,9 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, enum pci_barno bar, 
		if (is_64bits && (bar & 1))

			return -EINVAL;



		if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))

			epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;



		if (is_64bits && is_prefetch)

			ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;

		else if (is_prefetch)
@@ -139,10 +145,11 @@ static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, enum pci_barno bar, 
}



static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,

				   enum pci_barno bar)

				   struct pci_epf_bar *epf_bar)

{

	struct cdns_pcie_ep *ep = epc_get_drvdata(epc);

	struct cdns_pcie *pcie = &ep->pcie;

	enum pci_barno bar = epf_bar->barno;

	u32 reg, cfg, b, ctrl;



	if (bar < BAR_4) {

drivers/pci/dwc/pcie-designware-ep.c

+27 −7
Original line number Diff line number Diff line
@@ -19,7 +19,8 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) 
	pci_epc_linkup(epc);

}



void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)

static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,

				   int flags)

{

	u32 reg;
@@ -27,9 +28,18 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar) 
	dw_pcie_dbi_ro_wr_en(pci);

	dw_pcie_writel_dbi2(pci, reg, 0x0);

	dw_pcie_writel_dbi(pci, reg, 0x0);

	if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {

		dw_pcie_writel_dbi2(pci, reg + 4, 0x0);

		dw_pcie_writel_dbi(pci, reg + 4, 0x0);

	}

	dw_pcie_dbi_ro_wr_dis(pci);

}



void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)

{

	__dw_pcie_ep_reset_bar(pci, bar, 0);

}



static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,

				   struct pci_epf_header *hdr)

{
@@ -104,25 +114,28 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr, 
}



static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,

				 enum pci_barno bar)

				 struct pci_epf_bar *epf_bar)

{

	struct dw_pcie_ep *ep = epc_get_drvdata(epc);

	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);

	enum pci_barno bar = epf_bar->barno;

	u32 atu_index = ep->bar_to_atu[bar];



	dw_pcie_ep_reset_bar(pci, bar);

	__dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);



	dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);

	clear_bit(atu_index, ep->ib_window_map);

}



static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,

			      enum pci_barno bar,

			      dma_addr_t bar_phys, size_t size, int flags)

			      struct pci_epf_bar *epf_bar)

{

	int ret;

	struct dw_pcie_ep *ep = epc_get_drvdata(epc);

	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);

	enum pci_barno bar = epf_bar->barno;

	size_t size = epf_bar->size;

	int flags = epf_bar->flags;

	enum dw_pcie_as_type as_type;

	u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
@@ -131,13 +144,20 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, 
	else

		as_type = DW_PCIE_AS_IO;



	ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);

	ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type);

	if (ret)

		return ret;



	dw_pcie_dbi_ro_wr_en(pci);

	dw_pcie_writel_dbi2(pci, reg, size - 1);



	dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));

	dw_pcie_writel_dbi(pci, reg, flags);



	if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {

		dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));

		dw_pcie_writel_dbi(pci, reg + 4, 0);

	}



	dw_pcie_dbi_ro_wr_dis(pci);



	return 0;

drivers/pci/endpoint/functions/pci-epf-test.c

+18 −10
Original line number Diff line number Diff line
@@ -70,7 +70,7 @@ struct pci_epf_test_data { 
	bool		linkup_notifier;

};



static int bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };

static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };



static int pci_epf_test_copy(struct pci_epf_test *epf_test)

{
@@ -344,21 +344,23 @@ static void pci_epf_test_unbind(struct pci_epf *epf) 
{

	struct pci_epf_test *epf_test = epf_get_drvdata(epf);

	struct pci_epc *epc = epf->epc;

	struct pci_epf_bar *epf_bar;

	int bar;



	cancel_delayed_work(&epf_test->cmd_handler);

	pci_epc_stop(epc);

	for (bar = BAR_0; bar <= BAR_5; bar++) {

		epf_bar = &epf->bar[bar];



		if (epf_test->reg[bar]) {

			pci_epf_free_space(epf, epf_test->reg[bar], bar);

			pci_epc_clear_bar(epc, epf->func_no, bar);

			pci_epc_clear_bar(epc, epf->func_no, epf_bar);

		}

	}

}



static int pci_epf_test_set_bar(struct pci_epf *epf)

{

	int flags;

	int bar;

	int ret;

	struct pci_epf_bar *epf_bar;
@@ -367,21 +369,27 @@ static int pci_epf_test_set_bar(struct pci_epf *epf) 
	struct pci_epf_test *epf_test = epf_get_drvdata(epf);

	enum pci_barno test_reg_bar = epf_test->test_reg_bar;



	flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32;

	if (sizeof(dma_addr_t) == 0x8)

		flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;



	for (bar = BAR_0; bar <= BAR_5; bar++) {

		epf_bar = &epf->bar[bar];

		ret = pci_epc_set_bar(epc, epf->func_no, bar,

				      epf_bar->phys_addr,

				      epf_bar->size, flags);



		epf_bar->flags |= upper_32_bits(epf_bar->size) ?

			PCI_BASE_ADDRESS_MEM_TYPE_64 :

			PCI_BASE_ADDRESS_MEM_TYPE_32;



		ret = pci_epc_set_bar(epc, epf->func_no, epf_bar);

		if (ret) {

			pci_epf_free_space(epf, epf_test->reg[bar], bar);

			dev_err(dev, "failed to set BAR%d\n", bar);

			if (bar == test_reg_bar)

				return ret;

		}

		/*

		 * pci_epc_set_bar() sets PCI_BASE_ADDRESS_MEM_TYPE_64

		 * if the specific implementation required a 64-bit BAR,

		 * even if we only requested a 32-bit BAR.

		 */

		if (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)

			bar++;

	}



	return 0;

drivers/pci/endpoint/pci-epc-core.c

+20 −12
Original line number Diff line number Diff line
@@ -276,22 +276,25 @@ EXPORT_SYMBOL_GPL(pci_epc_map_addr); 
 * pci_epc_clear_bar() - reset the BAR

 * @epc: the EPC device for which the BAR has to be cleared

 * @func_no: the endpoint function number in the EPC device

 * @bar: the BAR number that has to be reset

 * @epf_bar: the struct epf_bar that contains the BAR information

 *

 * Invoke to reset the BAR of the endpoint device.

 */

void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, int bar)

void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,

		       struct pci_epf_bar *epf_bar)

{

	unsigned long flags;



	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)

	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||

	    (epf_bar->barno == BAR_5 &&

	     epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64))

		return;



	if (!epc->ops->clear_bar)

		return;



	spin_lock_irqsave(&epc->lock, flags);

	epc->ops->clear_bar(epc, func_no, bar);

	epc->ops->clear_bar(epc, func_no, epf_bar);

	spin_unlock_irqrestore(&epc->lock, flags);

}

EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
@@ -300,26 +303,31 @@ EXPORT_SYMBOL_GPL(pci_epc_clear_bar); 
 * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space

 * @epc: the EPC device on which BAR has to be configured

 * @func_no: the endpoint function number in the EPC device

 * @bar: the BAR number that has to be configured

 * @size: the size of the addr space

 * @flags: specify memory allocation/io allocation/32bit address/64 bit address

 * @epf_bar: the struct epf_bar that contains the BAR information

 *

 * Invoke to configure the BAR of the endpoint device.

 */

int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, enum pci_barno bar,

		    dma_addr_t bar_phys, size_t size, int flags)

int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,

		    struct pci_epf_bar *epf_bar)

{

	int ret;

	unsigned long irq_flags;



	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)

	int flags = epf_bar->flags;



	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||

	    (epf_bar->barno == BAR_5 &&

	     flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ||

	    (flags & PCI_BASE_ADDRESS_SPACE_IO &&

	     flags & PCI_BASE_ADDRESS_IO_MASK) ||

	    (upper_32_bits(epf_bar->size) &&

	     !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))

		return -EINVAL;



	if (!epc->ops->set_bar)

		return 0;



	spin_lock_irqsave(&epc->lock, irq_flags);

	ret = epc->ops->set_bar(epc, func_no, bar, bar_phys, size, flags);

	ret = epc->ops->set_bar(epc, func_no, epf_bar);

	spin_unlock_irqrestore(&epc->lock, irq_flags);



	return ret;