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Commit 14be9947 authored by Bob Copeland's avatar Bob Copeland Committed by John W. Linville
Browse files

ath5k: write beacon control register twice when resetting tsf 



According to the newly-released Atheros HAL code, asserting the
TSF reset bit will toggle a hardware internal state, resulting in a
spurious reset on the next chip reset.  Whenever we force a TSF bit,
write the bit twice to clear the internal signal.

Signed-off-by: default avatarBob Copeland <me@bobcopeland.com>
Acked-by: default avatarNick Kossifidis <mickflemm@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent b0dee578

drivers/net/wireless/ath5k/pcu.c

+13 −1
Original line number Diff line number Diff line
@@ -633,8 +633,20 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah) 
 */

void ath5k_hw_reset_tsf(struct ath5k_hw *ah)

{

	u32 val;



	ATH5K_TRACE(ah->ah_sc);

	AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);



	val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;



	/*

	 * Each write to the RESET_TSF bit toggles a hardware internal

	 * signal to reset TSF, but if left high it will cause a TSF reset

	 * on the next chip reset as well.  Thus we always write the value

	 * twice to clear the signal.

	 */

	ath5k_hw_reg_write(ah, val, AR5K_BEACON);

	ath5k_hw_reg_write(ah, val, AR5K_BEACON);

}



/*