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Commit 149c5d79 authored by Mohammed Siddiq's avatar Mohammed Siddiq Committed by Gerrit - the friendly Code Review server
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cnss2: Remove hard-code address for error log start for HST 



Remove hard-code address for error log start for HST as
in HST device side change is added to enable for the error
log start address and size to be shared via ERRDBG2 and
ERRDBG3 registers respectfully.

Change-Id: I1e0cadf49bcbb82353f8f3140d6c144ef3237a9b
Signed-off-by: default avatarMohammed Siddiq <msiddiq@codeaurora.org>
parent 0e84d960

drivers/net/wireless/cnss2/pci.c

+23 −7
Original line number Diff line number Diff line
@@ -1706,7 +1706,7 @@ static void cnss_pci_collect_dump(struct cnss_pci_data *pci_priv) 
static void cnss_pci_dump_qca6390_sram_mem(struct cnss_pci_data *pci_priv)

{

	int i;

	u32 mem_addr, val, pbl_stage;

	u32 mem_addr, val, pbl_stage, sbl_log_start, sbl_log_size;

	u32 pbl_wlan_boot_cfg, pbl_bootstrap_status;

	struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
@@ -1717,15 +1717,20 @@ static void cnss_pci_dump_qca6390_sram_mem(struct cnss_pci_data *pci_priv) 
		return;



	cnss_pci_reg_read(pci_priv, QCA6390_TCSR_PBL_LOGGING_REG, &pbl_stage);

	cnss_pci_reg_read(pci_priv, QCA6390_PCIE_BHI_ERRDBG2_REG,

			  &sbl_log_start);

	cnss_pci_reg_read(pci_priv, QCA6390_PCIE_BHI_ERRDBG3_REG,

			  &sbl_log_size);

	cnss_pci_reg_read(pci_priv, QCA6390_PBL_WLAN_BOOT_CFG,

			  &pbl_wlan_boot_cfg);

	cnss_pci_reg_read(pci_priv, QCA6390_PBL_BOOTSTRAP_STATUS,

			  &pbl_bootstrap_status);

	cnss_pr_dbg("TCSR_PBL_LOGGING: 0x%08x", pbl_stage);

	cnss_pr_dbg("PBL_WLAN_BOOT_CFG: 0x%08x PBL_BOOTSTRAP_STATUS: 0x%08x",

	cnss_pr_dbg("TCSR_PBL_LOGGING: 0x%08x PCIE_BHI_ERRDBG: Start: 0x%08x Size:0x%08x\n",

		    pbl_stage, sbl_log_start, sbl_log_size);

	cnss_pr_dbg("PBL_WLAN_BOOT_CFG: 0x%08x PBL_BOOTSTRAP_STATUS: 0x%08x\n",

		    pbl_wlan_boot_cfg, pbl_bootstrap_status);



	cnss_pr_dbg("Dumping PBL log data");

	cnss_pr_dbg("Dumping PBL log data\n");

	/* cnss_pci_reg_read provides 32bit register values */

	for (i = 0; i < QCA6390_DEBUG_PBL_LOG_SRAM_MAX_SIZE; i += sizeof(val)) {

		mem_addr = QCA6390_DEBUG_PBL_LOG_SRAM_START + i;
@@ -1734,13 +1739,24 @@ static void cnss_pci_dump_qca6390_sram_mem(struct cnss_pci_data *pci_priv) 
		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);

	}



	cnss_pr_dbg("Dumping SBL log data");

	for (i = 0; i < QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE; i += sizeof(val)) {

		mem_addr = QCA6390_V2_SBL_DATA_START + i;

	sbl_log_size = (sbl_log_size > QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE ?

			QCA6390_DEBUG_SBL_LOG_SRAM_MAX_SIZE : sbl_log_size);



	if (sbl_log_start < QCA6390_V2_SBL_DATA_START ||

	    sbl_log_start > QCA6390_V2_SBL_DATA_END ||

	    (sbl_log_start + sbl_log_size) > QCA6390_V2_SBL_DATA_END)

		goto out;



	cnss_pr_dbg("Dumping SBL log data\n");

	for (i = 0; i < sbl_log_size; i += sizeof(val)) {

		mem_addr = sbl_log_start + i;

		if (cnss_pci_reg_read(pci_priv, mem_addr, &val))

			break;

		cnss_pr_dbg("SRAM[0x%x] = 0x%x\n", mem_addr, val);

	}

	return;

out:

	cnss_pr_err("Invalid SBL log data\n");

}



/**