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Commit 144659b9 authored by Karthikeyan Mani's avatar Karthikeyan Mani
Browse files

asoc: codecs: bolero: toggle zero gate for first hpf update 



Instead of disabling hpf zero gate in hpf callback,
disable it while setting the inital cut off frequency
itself to not have any glitches.

Change-Id: I932aa0b2d68c2e8afd5cddd3d5fe17cbc98a5afb
Signed-off-by: default avatarKarthikeyan Mani <kmani@codeaurora.org>
parent ae5dca48

asoc/codecs/bolero/tx-macro.c

+7 −3
Original line number Diff line number Diff line
@@ -450,10 +450,10 @@ static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 
	snd_soc_component_update_bits(component,

			dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,

			hpf_cut_off_freq << 5);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x02);

	/* Minimum 1 clk cycle delay is required as per HW spec */

	usleep_range(1000, 1010);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x01);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00);

}



static void tx_macro_mute_update_callback(struct work_struct *work)
@@ -865,6 +865,10 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
			tx_vol_ctl_reg, 0x20, 0x20);

		snd_soc_component_update_bits(component,

			hpf_gate_reg, 0x01, 0x00);

		/*

		 * Minimum 1 clk cycle delay is required as per HW spec

		 */

		usleep_range(1000, 1010);



		hpf_cut_off_freq = (

			snd_soc_component_read32(component, dec_cfg_reg) &
@@ -887,7 +891,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
					&tx_priv->tx_hpf_work[decimator].dwork,

					msecs_to_jiffies(300));

			snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x02, 0x02);

					hpf_gate_reg, 0x03, 0x03);

			/*

			 * Minimum 1 clk cycle delay is required as per HW spec

			 */

asoc/codecs/bolero/va-macro.c

+7 −3
Original line number Diff line number Diff line
@@ -393,10 +393,10 @@ static void va_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 
	snd_soc_component_update_bits(component,

			dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,

			hpf_cut_off_freq << 5);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x02);

	/* Minimum 1 clk cycle delay is required as per HW spec */

	usleep_range(1000, 1010);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x01);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00);

}



static void va_macro_mute_update_callback(struct work_struct *work)
@@ -688,6 +688,10 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				tx_vol_ctl_reg, 0x20, 0x20);

		snd_soc_component_update_bits(component,

				hpf_gate_reg, 0x01, 0x00);

		/*

		 * Minimum 1 clk cycle delay is required as per HW spec

		 */

		usleep_range(1000, 1010);



		hpf_cut_off_freq = (snd_soc_component_read32(

					component, dec_cfg_reg) &
@@ -700,7 +704,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
					    TX_HPF_CUT_OFF_FREQ_MASK,

					    CF_MIN_3DB_150HZ << 5);

			snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x02, 0x02);

					hpf_gate_reg, 0x03, 0x03);

			/*

			 * Minimum 1 clk cycle delay is required as per HW spec

			 */