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Commit 142ea05f authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/gr: switch to gpuobj accessor macros 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 5444e770

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c

+21 −16
Original line number Diff line number Diff line
@@ -1289,27 +1289,28 @@ gf100_grctx_generate(struct gf100_gr *gr) 
	}



	/* PGD pointer */

	nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000));

	nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000));

	nv_wo32(chan, 0x0208, 0xffffffff);

	nv_wo32(chan, 0x020c, 0x000000ff);

	nvkm_kmap(chan);

	nvkm_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000));

	nvkm_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000));

	nvkm_wo32(chan, 0x0208, 0xffffffff);

	nvkm_wo32(chan, 0x020c, 0x000000ff);



	/* PGT[0] pointer */

	nv_wo32(chan, 0x1000, 0x00000000);

	nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8);

	nvkm_wo32(chan, 0x1000, 0x00000000);

	nvkm_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8);



	/* identity-map the whole "channel" into its own vm */

	for (i = 0; i < chan->size / 4096; i++) {

		u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1;

		nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr));

		nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr));

		nvkm_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr));

		nvkm_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr));

	}



	/* context pointer (virt) */

	nv_wo32(chan, 0x0210, 0x00080004);

	nv_wo32(chan, 0x0214, 0x00000000);



	nvkm_wo32(chan, 0x0210, 0x00080004);

	nvkm_wo32(chan, 0x0214, 0x00000000);

	bar->flush(bar);

	nvkm_done(chan);



	nvkm_wr32(device, 0x100cb8, (chan->addr + 0x1000) >> 8);

	nvkm_wr32(device, 0x100cbc, 0x80000001);
@@ -1335,11 +1336,13 @@ gf100_grctx_generate(struct gf100_gr *gr) 
				break;

		);



		nv_wo32(chan, 0x8001c, 1);

		nv_wo32(chan, 0x80020, 0);

		nv_wo32(chan, 0x80028, 0);

		nv_wo32(chan, 0x8002c, 0);

		nvkm_kmap(chan);

		nvkm_wo32(chan, 0x8001c, 1);

		nvkm_wo32(chan, 0x80020, 0);

		nvkm_wo32(chan, 0x80028, 0);

		nvkm_wo32(chan, 0x8002c, 0);

		bar->flush(bar);

		nvkm_done(chan);

	} else {

		nvkm_wr32(device, 0x409840, 0x80000000);

		nvkm_wr32(device, 0x409500, 0x80000000 | chan->addr >> 12);
@@ -1367,8 +1370,10 @@ gf100_grctx_generate(struct gf100_gr *gr) 


	gr->data = kmalloc(gr->size, GFP_KERNEL);

	if (gr->data) {

		nvkm_kmap(chan);

		for (i = 0; i < gr->size; i += 4)

			gr->data[i / 4] = nv_ro32(chan, 0x80000 + i);

			gr->data[i / 4] = nvkm_ro32(chan, 0x80000 + i);

		nvkm_done(chan);

		ret = 0;

	} else {

		ret = -ENOMEM;

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c

+6 −4
Original line number Diff line number Diff line
@@ -580,16 +580,18 @@ nv40_gr_construct_shader(struct nvkm_grctx *ctx) 
	if (ctx->mode != NVKM_GRCTX_VALS)

		return;



	nvkm_kmap(obj);

	offset += 0x0280/4;

	for (i = 0; i < 16; i++, offset += 2)

		nv_wo32(obj, offset * 4, 0x3f800000);

		nvkm_wo32(obj, offset * 4, 0x3f800000);



	for (vs = 0; vs < vs_nr; vs++, offset += vs_len) {

		for (i = 0; i < vs_nr_b0 * 6; i += 6)

			nv_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001);

			nvkm_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001);

		for (i = 0; i < vs_nr_b1 * 4; i += 4)

			nv_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000);

			nvkm_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000);

	}

	nvkm_done(obj);

}



static void
@@ -674,7 +676,7 @@ nv40_grctx_init(struct nvkm_device *device, u32 *size) 
	struct nvkm_grctx ctx = {

		.device = device,

		.mode = NVKM_GRCTX_PROG,

		.data = ctxprog,

		.ucode = ctxprog,

		.ctxprog_max = 256,

	};

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h

+7 −4
Original line number Diff line number Diff line
@@ -9,7 +9,8 @@ struct nvkm_grctx { 
		NVKM_GRCTX_PROG,

		NVKM_GRCTX_VALS

	} mode;

	void *data;

	u32 *ucode;

	struct nvkm_gpuobj *data;



	u32 ctxprog_max;

	u32 ctxprog_len;
@@ -22,7 +23,7 @@ struct nvkm_grctx { 
static inline void

cp_out(struct nvkm_grctx *ctx, u32 inst)

{

	u32 *ctxprog = ctx->data;

	u32 *ctxprog = ctx->ucode;



	if (ctx->mode != NVKM_GRCTX_PROG)

		return;
@@ -56,7 +57,7 @@ cp_ctx(struct nvkm_grctx *ctx, u32 reg, u32 length) 
static inline void

cp_name(struct nvkm_grctx *ctx, int name)

{

	u32 *ctxprog = ctx->data;

	u32 *ctxprog = ctx->ucode;

	int i;



	if (ctx->mode != NVKM_GRCTX_PROG)
@@ -124,6 +125,8 @@ gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val) 
	reg = (reg - 0x00400000) / 4;

	reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base;



	nv_wo32(ctx->data, reg * 4, val);

	nvkm_kmap(ctx->data);

	nvkm_wo32(ctx->data, reg * 4, val);

	nvkm_done(ctx->data);

}

#endif

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c

+11 −5
Original line number Diff line number Diff line
@@ -268,7 +268,7 @@ nv50_grctx_init(struct nvkm_device *device, u32 *size) 
	struct nvkm_grctx ctx = {

		.device = device,

		.mode = NVKM_GRCTX_PROG,

		.data = ctxprog,

		.ucode = ctxprog,

		.ctxprog_max = 512,

	};
@@ -783,9 +783,12 @@ nv50_gr_construct_mmio(struct nvkm_grctx *ctx) 
static void

dd_emit(struct nvkm_grctx *ctx, int num, u32 val) {

	int i;

	if (val && ctx->mode == NVKM_GRCTX_VALS)

	if (val && ctx->mode == NVKM_GRCTX_VALS) {

		nvkm_kmap(ctx->data);

		for (i = 0; i < num; i++)

			nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val);

			nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val);

		nvkm_done(ctx->data);

	}

	ctx->ctxvals_pos += num;

}
@@ -1155,9 +1158,12 @@ nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx) 
static void

xf_emit(struct nvkm_grctx *ctx, int num, u32 val) {

	int i;

	if (val && ctx->mode == NVKM_GRCTX_VALS)

	if (val && ctx->mode == NVKM_GRCTX_VALS) {

		nvkm_kmap(ctx->data);

		for (i = 0; i < num; i++)

			nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val);

			nvkm_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val);

		nvkm_done(ctx->data);

	}

	ctx->ctxvals_pos += num << 3;

}

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

+29 −18
Original line number Diff line number Diff line
@@ -283,6 +283,7 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
	struct gf100_gr_data *data = gr->mmio_data;

	struct gf100_gr_mmio *mmio = gr->mmio_list;

	struct gf100_gr_chan *chan;

	struct nvkm_gpuobj *image;

	int ret, i;



	/* allocate memory for context, and fill with default values */
@@ -324,6 +325,7 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
	}



	/* finally, fill in the mmio list and point the context at it */

	nvkm_kmap(chan->mmio);

	for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) {

		u32 addr = mmio->addr;

		u32 data = mmio->data;
@@ -333,28 +335,32 @@ gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
			data |= info >> mmio->shift;

		}



		nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);

		nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data);

		nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);

		nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data);

		mmio++;

	}

	nvkm_done(chan->mmio);



	image = &chan->base.base.gpuobj;

	nvkm_kmap(image);

	for (i = 0; i < gr->size; i += 4)

		nv_wo32(chan, i, gr->data[i / 4]);

		nvkm_wo32(image, i, gr->data[i / 4]);



	if (!gr->firmware) {

		nv_wo32(chan, 0x00, chan->mmio_nr / 2);

		nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8);

		nvkm_wo32(image, 0x00, chan->mmio_nr / 2);

		nvkm_wo32(image, 0x04, chan->mmio_vma.offset >> 8);

	} else {

		nv_wo32(chan, 0xf4, 0);

		nv_wo32(chan, 0xf8, 0);

		nv_wo32(chan, 0x10, chan->mmio_nr / 2);

		nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset));

		nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset));

		nv_wo32(chan, 0x1c, 1);

		nv_wo32(chan, 0x20, 0);

		nv_wo32(chan, 0x28, 0);

		nv_wo32(chan, 0x2c, 0);

	}

		nvkm_wo32(image, 0xf4, 0);

		nvkm_wo32(image, 0xf8, 0);

		nvkm_wo32(image, 0x10, chan->mmio_nr / 2);

		nvkm_wo32(image, 0x14, lower_32_bits(chan->mmio_vma.offset));

		nvkm_wo32(image, 0x18, upper_32_bits(chan->mmio_vma.offset));

		nvkm_wo32(image, 0x1c, 1);

		nvkm_wo32(image, 0x20, 0);

		nvkm_wo32(image, 0x28, 0);

		nvkm_wo32(image, 0x2c, 0);

	}

	nvkm_done(image);



	return 0;

}
@@ -1679,10 +1685,15 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 
	if (ret)

		return ret;



	for (i = 0; i < 0x1000; i += 4) {

		nv_wo32(gr->unk4188b4, i, 0x00000010);

		nv_wo32(gr->unk4188b8, i, 0x00000010);

	}

	nvkm_kmap(gr->unk4188b4);

	for (i = 0; i < 0x1000; i += 4)

		nvkm_wo32(gr->unk4188b4, i, 0x00000010);

	nvkm_done(gr->unk4188b4);



	nvkm_kmap(gr->unk4188b8);

	for (i = 0; i < 0x1000; i += 4)

		nvkm_wo32(gr->unk4188b8, i, 0x00000010);

	nvkm_done(gr->unk4188b8);



	gr->rop_nr = (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16;

	gr->gpc_nr =  nvkm_rd32(device, 0x409604) & 0x0000001f;