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Commit 1409ce03 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'socfpga_dts_for_v4.12' of... 

Merge tag 'socfpga_dts_for_v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA DTS updates for v4.12
- Clean-up:
	- Add clock/memory nodes
	- Add labels for CPU nodes
	- Remove unused unit names and reg
	- Remove unused skeleton.dtsi
- Add support for PMU
- Add QSPI for sodia board
- Add Reset controller for Arria10

* tag 'socfpga_dts_for_v4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux

:
  ARM: dts: socfpga: Add Devkit A10-SR Reset Controller
  ARM: dts: socfpga: sodia: enable qspi
  ARM: dts: socfpga: Add support for PMU
  ARM: dts: socfpga: Add labels for CPU nodes
  ARM: dts: socfpga: Do not include skeleton.dtsi
  ARM: dts: socfpga: Remove unit name for LEDs in EBV SOCrates
  ARM: dts: socfpga: Remove unneeded reg from stmpe_touchscreen
  ARM: dts: socfpga: Remove unneeded unit names
  ARM: dts: socfpga: Add unit name to memory nodes
  ARM: dts: socfpga: Add unit name to clock nodes

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents b68d58a8 7fed0cbf

arch/arm/boot/dts/socfpga.dtsi

+32 −24
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@ 
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include "skeleton.dtsi"

#include <dt-bindings/reset/altr,rst-mgr.h>



/ {
@@ -38,13 +37,13 @@ 
		#size-cells = <0>;

		enable-method = "altr,socfpga-smp";



		cpu@0 {

		cpu0: cpu@0 {

			compatible = "arm,cortex-a9";

			device_type = "cpu";

			reg = <0>;

			next-level-cache = <&L2>;

		};

		cpu@1 {

		cpu1: cpu@1 {

			compatible = "arm,cortex-a9";

			device_type = "cpu";

			reg = <1>;
@@ -52,6 +51,15 @@ 
		};

	};



	pmu: pmu@ff111000 {

		compatible = "arm,cortex-a9-pmu";

		interrupt-parent = <&intc>;

		interrupts = <0 176 4>, <0 177 4>;

		interrupt-affinity = <&cpu0>, <&cpu1>;

		reg = <0xff111000 0x1000>,

		      <0xff113000 0x1000>;

	};



	intc: intc@fffed000 {

		compatible = "arm,cortex-a9-gic";

		#interrupt-cells = <3>;
@@ -145,7 +153,7 @@ 
						compatible = "fixed-clock";

					};



					main_pll: main_pll {

					main_pll: main_pll@40 {

						#address-cells = <1>;

						#size-cells = <0>;

						#clock-cells = <0>;
@@ -153,7 +161,7 @@ 
						clocks = <&osc1>;

						reg = <0x40>;



						mpuclk: mpuclk {

						mpuclk: mpuclk@48 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;
@@ -161,7 +169,7 @@ 
							reg = <0x48>;

						};



						mainclk: mainclk {

						mainclk: mainclk@4c {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;
@@ -169,7 +177,7 @@ 
							reg = <0x4C>;

						};



						dbg_base_clk: dbg_base_clk {

						dbg_base_clk: dbg_base_clk@50 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>, <&osc1>;
@@ -177,21 +185,21 @@ 
							reg = <0x50>;

						};



						main_qspi_clk: main_qspi_clk {

						main_qspi_clk: main_qspi_clk@54 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;

							reg = <0x54>;

						};



						main_nand_sdmmc_clk: main_nand_sdmmc_clk {

						main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;

							reg = <0x58>;

						};



						cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {

						cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&main_pll>;
@@ -199,7 +207,7 @@ 
						};

					};



					periph_pll: periph_pll {

					periph_pll: periph_pll@80 {

						#address-cells = <1>;

						#size-cells = <0>;

						#clock-cells = <0>;
@@ -207,42 +215,42 @@ 
						clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;

						reg = <0x80>;



						emac0_clk: emac0_clk {

						emac0_clk: emac0_clk@88 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&periph_pll>;

							reg = <0x88>;

						};



						emac1_clk: emac1_clk {

						emac1_clk: emac1_clk@8c {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&periph_pll>;

							reg = <0x8C>;

						};



						per_qspi_clk: per_qsi_clk {

						per_qspi_clk: per_qsi_clk@90 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&periph_pll>;

							reg = <0x90>;

						};



						per_nand_mmc_clk: per_nand_mmc_clk {

						per_nand_mmc_clk: per_nand_mmc_clk@94 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&periph_pll>;

							reg = <0x94>;

						};



						per_base_clk: per_base_clk {

						per_base_clk: per_base_clk@98 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&periph_pll>;

							reg = <0x98>;

						};



						h2f_usr1_clk: h2f_usr1_clk {

						h2f_usr1_clk: h2f_usr1_clk@9c {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&periph_pll>;
@@ -250,7 +258,7 @@ 
						};

					};



					sdram_pll: sdram_pll {

					sdram_pll: sdram_pll@c0 {

						#address-cells = <1>;

						#size-cells = <0>;

						#clock-cells = <0>;
@@ -258,28 +266,28 @@ 
						clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;

						reg = <0xC0>;



						ddr_dqs_clk: ddr_dqs_clk {

						ddr_dqs_clk: ddr_dqs_clk@c8 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&sdram_pll>;

							reg = <0xC8>;

						};



						ddr_2x_dqs_clk: ddr_2x_dqs_clk {

						ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&sdram_pll>;

							reg = <0xCC>;

						};



						ddr_dq_clk: ddr_dq_clk {

						ddr_dq_clk: ddr_dq_clk@d0 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&sdram_pll>;

							reg = <0xD0>;

						};



						h2f_usr2_clk: h2f_usr2_clk {

						h2f_usr2_clk: h2f_usr2_clk@d4 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-perip-clk";

							clocks = <&sdram_pll>;
@@ -678,7 +686,7 @@ 
			status = "disabled";

		};



		eccmgr: eccmgr@ffd08140 {

		eccmgr: eccmgr {

			compatible = "altr,socfpga-ecc-manager";

			#address-cells = <1>;

			#size-cells = <1>;
@@ -879,7 +887,7 @@ 
			dma-names = "tx", "rx";

		};



		usbphy0: usbphy@0 {

		usbphy0: usbphy {

			#phy-cells = <0>;

			compatible = "usb-nop-xceiv";

			status = "okay";

arch/arm/boot/dts/socfpga_arria10.dtsi

+25 −26
Original line number Diff line number Diff line
@@ -14,7 +14,6 @@ 
 * this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#include "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/reset/altr,rst-mgr-a10.h>
@@ -119,7 +118,7 @@ 
						compatible = "fixed-clock";

					};



					main_pll: main_pll {

					main_pll: main_pll@40 {

						#address-cells = <1>;

						#size-cells = <0>;

						#clock-cells = <0>;
@@ -142,35 +141,35 @@ 
							div-reg = <0x144 0 11>;

						};



						main_emaca_clk: main_emaca_clk {

						main_emaca_clk: main_emaca_clk@68 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&main_pll>;

							reg = <0x68>;

						};



						main_emacb_clk: main_emacb_clk {

						main_emacb_clk: main_emacb_clk@6c {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&main_pll>;

							reg = <0x6C>;

						};



						main_emac_ptp_clk: main_emac_ptp_clk {

						main_emac_ptp_clk: main_emac_ptp_clk@70 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&main_pll>;

							reg = <0x70>;

						};



						main_gpio_db_clk: main_gpio_db_clk {

						main_gpio_db_clk: main_gpio_db_clk@74 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&main_pll>;

							reg = <0x74>;

						};



						main_sdmmc_clk: main_sdmmc_clk {

						main_sdmmc_clk: main_sdmmc_clk@78 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk"

;
@@ -178,28 +177,28 @@ 
							reg = <0x78>;

						};



						main_s2f_usr0_clk: main_s2f_usr0_clk {

						main_s2f_usr0_clk: main_s2f_usr0_clk@7c {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&main_pll>;

							reg = <0x7C>;

						};



						main_s2f_usr1_clk: main_s2f_usr1_clk {

						main_s2f_usr1_clk: main_s2f_usr1_clk@80 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&main_pll>;

							reg = <0x80>;

						};



						main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {

						main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&main_pll>;

							reg = <0x84>;

						};



						main_periph_ref_clk: main_periph_ref_clk {

						main_periph_ref_clk: main_periph_ref_clk@9c {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&main_pll>;
@@ -207,7 +206,7 @@ 
						};

					};



					periph_pll: periph_pll {

					periph_pll: periph_pll@c0 {

						#address-cells = <1>;

						#size-cells = <0>;

						#clock-cells = <0>;
@@ -230,56 +229,56 @@ 
							div-reg = <0x144 16 11>;

						};



						peri_emaca_clk: peri_emaca_clk {

						peri_emaca_clk: peri_emaca_clk@e8 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&periph_pll>;

							reg = <0xE8>;

						};



						peri_emacb_clk: peri_emacb_clk {

						peri_emacb_clk: peri_emacb_clk@ec {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&periph_pll>;

							reg = <0xEC>;

						};



						peri_emac_ptp_clk: peri_emac_ptp_clk {

						peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&periph_pll>;

							reg = <0xF0>;

						};



						peri_gpio_db_clk: peri_gpio_db_clk {

						peri_gpio_db_clk: peri_gpio_db_clk@f4 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&periph_pll>;

							reg = <0xF4>;

						};



						peri_sdmmc_clk: peri_sdmmc_clk {

						peri_sdmmc_clk: peri_sdmmc_clk@f8 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&periph_pll>;

							reg = <0xF8>;

						};



						peri_s2f_usr0_clk: peri_s2f_usr0_clk {

						peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&periph_pll>;

							reg = <0xFC>;

						};



						peri_s2f_usr1_clk: peri_s2f_usr1_clk {

						peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&periph_pll>;

							reg = <0x100>;

						};



						peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {

						peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {

							#clock-cells = <0>;

							compatible = "altr,socfpga-a10-perip-clk";

							clocks = <&periph_pll>;
@@ -287,7 +286,7 @@ 
						};

					};



					mpu_free_clk: mpu_free_clk {

					mpu_free_clk: mpu_free_clk@60 {

						#clock-cells = <0>;

						compatible = "altr,socfpga-a10-perip-clk";

						clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
@@ -296,7 +295,7 @@ 
						reg = <0x60>;

					};



					noc_free_clk: noc_free_clk {

					noc_free_clk: noc_free_clk@64 {

						#clock-cells = <0>;

						compatible = "altr,socfpga-a10-perip-clk";

						clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
@@ -305,7 +304,7 @@ 
						reg = <0x64>;

					};



					s2f_user1_free_clk: s2f_user1_free_clk {

					s2f_user1_free_clk: s2f_user1_free_clk@104 {

						#clock-cells = <0>;

						compatible = "altr,socfpga-a10-perip-clk";

						clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
@@ -314,7 +313,7 @@ 
						reg = <0x104>;

					};



					sdmmc_free_clk: sdmmc_free_clk {

					sdmmc_free_clk: sdmmc_free_clk@f8 {

						#clock-cells = <0>;

						compatible = "altr,socfpga-a10-perip-clk";

						clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
@@ -649,7 +648,7 @@ 
			reg = <0xffe00000 0x40000>;

		};



		eccmgr: eccmgr@ffd06000 {

		eccmgr: eccmgr {

			compatible = "altr,socfpga-a10-ecc-manager";

			altr,sysmgr-syscon = <&sysmgr>;

			#address-cells = <1>;
@@ -806,7 +805,7 @@ 
			status = "disabled";

		};



		usbphy0: usbphy@0 {

		usbphy0: usbphy {

			#phy-cells = <0>;

			compatible = "usb-nop-xceiv";

			status = "okay";

arch/arm/boot/dts/socfpga_arria10_socdk.dtsi

+6 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ 
		stdout-path = "serial0:115200n8";

	};



	memory {

	memory@0 {

		name = "memory";

		device_type = "memory";

		reg = <0x0 0x40000000>; /* 1GB */
@@ -121,6 +121,11 @@ 
			gpio-controller;

			#gpio-cells = <2>;

		};



		a10sr_rst: reset-controller {

			compatible = "altr,a10sr-reset";

			#reset-cells = <1>;

		};

	};

};

arch/arm/boot/dts/socfpga_arria5_socdk.dts

+1 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 
		stdout-path = "serial0:115200n8";

	};



	memory {

	memory@0 {

		name = "memory";

		device_type = "memory";

		reg = <0x0 0x40000000>; /* 1GB */

arch/arm/boot/dts/socfpga_cyclone5_de0_sockit.dts

+1 −1
Original line number Diff line number Diff line
@@ -25,7 +25,7 @@ 
		stdout-path = "serial0:115200n8";

	};



	memory {

	memory@0 {

		name = "memory";

		device_type = "memory";

		reg = <0x0 0x40000000>; /* 1GB */