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Commit 1408cc1f authored by Yuval Mintz's avatar Yuval Mintz Committed by David S. Miller
Browse files

qed: Introduce VFs 



This adds the qed VFs for the first time -
The vfs are limited functions, with a very different PCI bar structure
[when compared with PFs] to better impose the related security demands
associated with them.

This patch includes the logic neccesary to allow VFs to successfully probe
[without actually adding the ability to enable iov].
This includes diverging all the flows that would occur as part of the pci
probe of the driver, preventing VF from accessing registers/memories it
can't and instead utilize the VF->PF channel to query the PF for needed
information.

Signed-off-by: default avatarYuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 37bff2b9

drivers/net/ethernet/qlogic/qed/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -3,4 +3,4 @@ obj-$(CONFIG_QED) := qed.o 
qed-y := qed_cxt.o qed_dev.o qed_hw.o qed_init_fw_funcs.o qed_init_ops.o \

	 qed_int.o qed_main.o qed_mcp.o qed_sp_commands.o qed_spq.o qed_l2.o \

	 qed_selftest.o

qed-$(CONFIG_QED_SRIOV) += qed_sriov.o
 
qed-$(CONFIG_QED_SRIOV) += qed_sriov.o qed_vf.o

drivers/net/ethernet/qlogic/qed/qed.h

+5 −0
Original line number Diff line number Diff line
@@ -311,6 +311,8 @@ struct qed_hwfn { 
	bool				first_on_engine;

	bool				hw_init_done;



	u8				num_funcs_on_engine;



	/* BAR access */

	void __iomem			*regview;

	void __iomem			*doorbells;
@@ -361,6 +363,7 @@ struct qed_hwfn { 
	/* True if the driver requests for the link */

	bool				b_drv_link_init;



	struct qed_vf_iov		*vf_iov_info;

	struct qed_pf_iov		*pf_iov_info;

	struct qed_mcp_info		*mcp_info;
@@ -497,6 +500,8 @@ struct qed_dev { 
#define IS_QED_SRIOV(cdev)              (!!(cdev)->p_iov_info)



	unsigned long			tunn_mode;



	bool				b_is_vf;

	u32				drv_type;



	struct qed_eth_stats		*reset_stats;

drivers/net/ethernet/qlogic/qed/qed_cxt.c

+161 −25
Original line number Diff line number Diff line
@@ -24,11 +24,13 @@ 
#include "qed_hw.h"

#include "qed_init_ops.h"

#include "qed_reg_addr.h"

#include "qed_sriov.h"



/* Max number of connection types in HW (DQ/CDU etc.) */

#define MAX_CONN_TYPES		PROTOCOLID_COMMON

#define NUM_TASK_TYPES		2

#define NUM_TASK_PF_SEGMENTS	4

#define NUM_TASK_VF_SEGMENTS	1



/* QM constants */

#define QM_PQ_ELEMENT_SIZE	4 /* in bytes */
@@ -63,10 +65,12 @@ union conn_context { 
struct qed_conn_type_cfg {

	u32 cid_count;

	u32 cid_start;

	u32 cids_per_vf;

};



/* ILT Client configuration, Per connection type (protocol) resources. */

#define ILT_CLI_PF_BLOCKS	(1 + NUM_TASK_PF_SEGMENTS * 2)

#define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)

#define CDUC_BLK		(0)



enum ilt_clients {
@@ -97,6 +101,10 @@ struct qed_ilt_client_cfg { 
	/* ILT client blocks for PF */

	struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS];

	u32 pf_total_lines;



	/* ILT client blocks for VFs */

	struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS];

	u32 vf_total_lines;

};



/* Per Path -
@@ -123,6 +131,11 @@ struct qed_cxt_mngr { 
	/* computed ILT structure */

	struct qed_ilt_client_cfg	clients[ILT_CLI_MAX];



	/* total number of VFs for this hwfn -

	 * ALL VFs are symmetric in terms of HW resources

	 */

	u32				vf_count;



	/* Acquired CIDs */

	struct qed_cid_acquired_map	acquired[MAX_CONN_TYPES];
@@ -131,37 +144,60 @@ struct qed_cxt_mngr { 
	u32				pf_start_line;

};



static u32 qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr)

{

	u32 type, pf_cids = 0;

/* counts the iids for the CDU/CDUC ILT client configuration */

struct qed_cdu_iids {

	u32 pf_cids;

	u32 per_vf_cids;

};



	for (type = 0; type < MAX_CONN_TYPES; type++)

		pf_cids += p_mngr->conn_cfg[type].cid_count;

static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr,

			     struct qed_cdu_iids *iids)

{

	u32 type;



	return pf_cids;

	for (type = 0; type < MAX_CONN_TYPES; type++) {

		iids->pf_cids += p_mngr->conn_cfg[type].cid_count;

		iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;

	}

}



static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn,

			    struct qed_qm_iids *iids)

{

	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;

	int type;

	u32 vf_cids = 0, type;



	for (type = 0; type < MAX_CONN_TYPES; type++)

	for (type = 0; type < MAX_CONN_TYPES; type++) {

		iids->cids += p_mngr->conn_cfg[type].cid_count;

		vf_cids += p_mngr->conn_cfg[type].cids_per_vf;

	}



	DP_VERBOSE(p_hwfn, QED_MSG_ILT, "iids: CIDS %08x\n", iids->cids);

	iids->vf_cids += vf_cids * p_mngr->vf_count;

	DP_VERBOSE(p_hwfn, QED_MSG_ILT,

		   "iids: CIDS %08x vf_cids %08x\n",

		   iids->cids, iids->vf_cids);

}



/* set the iids count per protocol */

static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn,

					enum protocol_type type,

					u32 cid_count)

					u32 cid_count, u32 vf_cid_cnt)

{

	struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;

	struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];



	p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN);

	p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN);

}



u32 qed_cxt_get_proto_cid_count(struct qed_hwfn		*p_hwfn,

				enum protocol_type	type,

				u32			*vf_cid)

{

	if (vf_cid)

		*vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;



	return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;

}



static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli,
@@ -210,10 +246,12 @@ int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn) 
	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;

	struct qed_ilt_client_cfg *p_cli;

	struct qed_ilt_cli_blk *p_blk;

	u32 curr_line, total, pf_cids;

	struct qed_cdu_iids cdu_iids;

	struct qed_qm_iids qm_iids;

	u32 curr_line, total, i;



	memset(&qm_iids, 0, sizeof(qm_iids));

	memset(&cdu_iids, 0, sizeof(cdu_iids));



	p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT);
@@ -224,14 +262,16 @@ int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn) 
	/* CDUC */

	p_cli = &p_mngr->clients[ILT_CLI_CDUC];

	curr_line = p_mngr->pf_start_line;



	/* CDUC PF */

	p_cli->pf_total_lines = 0;



	/* get the counters for the CDUC and QM clients  */

	pf_cids = qed_cxt_cdu_iids(p_mngr);

	qed_cxt_cdu_iids(p_mngr, &cdu_iids);



	p_blk = &p_cli->pf_blks[CDUC_BLK];



	total = pf_cids * CONN_CXT_SIZE(p_hwfn);

	total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);



	qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,

			     total, CONN_CXT_SIZE(p_hwfn));
@@ -239,17 +279,36 @@ int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn) 
	qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);

	p_cli->pf_total_lines = curr_line - p_blk->start_line;



	/* CDUC VF */

	p_blk = &p_cli->vf_blks[CDUC_BLK];

	total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);



	qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line,

			     total, CONN_CXT_SIZE(p_hwfn));



	qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);

	p_cli->vf_total_lines = curr_line - p_blk->start_line;



	for (i = 1; i < p_mngr->vf_count; i++)

		qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,

				     ILT_CLI_CDUC);



	/* QM */

	p_cli = &p_mngr->clients[ILT_CLI_QM];

	p_blk = &p_cli->pf_blks[0];



	qed_cxt_qm_iids(p_hwfn, &qm_iids);

	total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids, 0, 0,

				   p_hwfn->qm_info.num_pqs, 0);



	DP_VERBOSE(p_hwfn, QED_MSG_ILT,

		   "QM ILT Info, (cids=%d, num_pqs=%d, memory_size=%d)\n",

		   qm_iids.cids, p_hwfn->qm_info.num_pqs, total);

	total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,

				   qm_iids.vf_cids, 0,

				   p_hwfn->qm_info.num_pqs,

				   p_hwfn->qm_info.num_vf_pqs);



	DP_VERBOSE(p_hwfn,

		   QED_MSG_ILT,

		   "QM ILT Info, (cids=%d, vf_cids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",

		   qm_iids.cids,

		   qm_iids.vf_cids,

		   p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);



	qed_ilt_cli_blk_fill(p_cli, p_blk,

			     curr_line, total * 0x1000,
@@ -358,7 +417,7 @@ static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn) 
	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;

	struct qed_ilt_client_cfg *clients = p_mngr->clients;

	struct qed_ilt_cli_blk *p_blk;

	u32 size, i, j;

	u32 size, i, j, k;

	int rc;



	size = qed_cxt_ilt_shadow_size(clients);
@@ -383,6 +442,16 @@ static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn) 
			if (rc != 0)

				goto ilt_shadow_fail;

		}

		for (k = 0; k < p_mngr->vf_count; k++) {

			for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {

				u32 lines = clients[i].vf_total_lines * k;



				p_blk = &clients[i].vf_blks[j];

				rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines);

				if (rc != 0)

					goto ilt_shadow_fail;

			}

		}

	}



	return 0;
@@ -467,6 +536,9 @@ int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn) 
	for (i = 0; i < ILT_CLI_MAX; i++)

		p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;



	if (p_hwfn->cdev->p_iov_info)

		p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs;



	/* Set the cxt mangr pointer priori to further allocations */

	p_hwfn->p_cxt_mngr = p_mngr;
@@ -579,8 +651,10 @@ void qed_qm_init_pf(struct qed_hwfn *p_hwfn) 
	params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port;

	params.is_first_pf = p_hwfn->first_on_engine;

	params.num_pf_cids = iids.cids;

	params.num_vf_cids = iids.vf_cids;

	params.start_pq = qm_info->start_pq;

	params.num_pf_pqs = qm_info->num_pqs;

	params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs;

	params.num_vf_pqs = qm_info->num_vf_pqs;

	params.start_vport = qm_info->start_vport;

	params.num_vports = qm_info->num_vports;

	params.pf_wfq = qm_info->pf_wfq;
@@ -610,26 +684,55 @@ static int qed_cm_init_pf(struct qed_hwfn *p_hwfn) 
static void qed_dq_init_pf(struct qed_hwfn *p_hwfn)

{

	struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;

	u32 dq_pf_max_cid = 0;

	u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;



	dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);



	dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);



	dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);



	dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);



	dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);



	dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);



	dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);



	dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);



	dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);



	/* 5 - PF */

	dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);



	dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);



	dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);

	STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);



	/* Connection types 6 & 7 are not in use, yet they must be configured

	 * as the highest possible connection. Not configuring them means the

	 * defaults will be  used, and with a large number of cids a bug may

	 * occur, if the defaults will be smaller than dq_pf_max_cid /

	 * dq_vf_max_cid.

	 */

	STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);

	STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);



	STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);

	STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);

}



static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn)
@@ -653,6 +756,38 @@ static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn) 
	}

}



static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn)

{

	struct qed_ilt_client_cfg *p_cli;

	u32 blk_factor;



	/* For simplicty  we set the 'block' to be an ILT page */

	if (p_hwfn->cdev->p_iov_info) {

		struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;



		STORE_RT_REG(p_hwfn,

			     PSWRQ2_REG_VF_BASE_RT_OFFSET,

			     p_iov->first_vf_in_pf);

		STORE_RT_REG(p_hwfn,

			     PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,

			     p_iov->first_vf_in_pf + p_iov->total_vfs);

	}



	p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];

	blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);

	if (p_cli->active) {

		STORE_RT_REG(p_hwfn,

			     PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,

			     blk_factor);

		STORE_RT_REG(p_hwfn,

			     PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,

			     p_cli->pf_total_lines);

		STORE_RT_REG(p_hwfn,

			     PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,

			     p_cli->vf_total_lines);

	}

}



/* ILT (PSWRQ2) PF */

static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn)

{
@@ -662,6 +797,7 @@ static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn) 
	u32 line, rt_offst, i;



	qed_ilt_bounds_init(p_hwfn);

	qed_ilt_vf_bounds_init(p_hwfn);



	p_mngr = p_hwfn->p_cxt_mngr;

	p_shdw = p_mngr->ilt_shadow;
@@ -839,10 +975,10 @@ int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn) 
	/* Set the number of required CORE connections */

	u32 core_cids = 1; /* SPQ */



	qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids);

	qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);



	qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,

				    p_params->num_cons);

				    p_params->num_cons, 1);



	return 0;

}

drivers/net/ethernet/qlogic/qed/qed_cxt.h

+3 −0
Original line number Diff line number Diff line
@@ -51,6 +51,9 @@ enum qed_cxt_elem_type { 
	QED_ELEM_TASK

};



u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn,

				enum protocol_type type, u32 *vf_cid);



/**

 * @brief qed_cxt_set_pf_params - Set the PF params for cxt init

 *

drivers/net/ethernet/qlogic/qed/qed_dev.c

+150 −32
Original line number Diff line number Diff line
@@ -43,8 +43,12 @@ static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 
{

	u32 bar_reg = (bar_id == BAR_ID_0 ?

		       PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE);

	u32	val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);

	u32 val;



	if (IS_VF(p_hwfn->cdev))

		return 1 << 17;



	val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg);

	if (val)

		return 1 << (val + 15);
@@ -114,6 +118,9 @@ void qed_resc_free(struct qed_dev *cdev) 
{

	int i;



	if (IS_VF(cdev))

		return;



	kfree(cdev->fw_data);

	cdev->fw_data = NULL;
@@ -144,14 +151,19 @@ void qed_resc_free(struct qed_dev *cdev) 


static int qed_init_qm_info(struct qed_hwfn *p_hwfn)

{

	u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0;

	struct qed_qm_info *qm_info = &p_hwfn->qm_info;

	struct init_qm_port_params *p_qm_port;

	u8 num_vports, i, vport_id, num_ports;

	u16 num_pqs, multi_cos_tcs = 1;

	u16 num_vfs = 0;



#ifdef CONFIG_QED_SRIOV

	if (p_hwfn->cdev->p_iov_info)

		num_vfs = p_hwfn->cdev->p_iov_info->total_vfs;

#endif

	memset(qm_info, 0, sizeof(*qm_info));



	num_pqs = multi_cos_tcs + 1; /* The '1' is for pure-LB */

	num_pqs = multi_cos_tcs + num_vfs + 1;	/* The '1' is for pure-LB */

	num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT);



	/* Sanity checking that setup requires legal number of resources */
@@ -187,8 +199,9 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn) 
	vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);



	/* First init per-TC PQs */

	for (i = 0; i < multi_cos_tcs; i++) {

		struct init_qm_pq_params *params = &qm_info->qm_pq_params[i];

	for (i = 0; i < multi_cos_tcs; i++, curr_queue++) {

		struct init_qm_pq_params *params =

		    &qm_info->qm_pq_params[curr_queue];



		params->vport_id = vport_id;

		params->tc_id = p_hwfn->hw_info.non_offload_tc;
@@ -196,13 +209,26 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn) 
	}



	/* Then init pure-LB PQ */

	qm_info->pure_lb_pq = i;

	qm_info->qm_pq_params[i].vport_id = (u8)RESC_START(p_hwfn, QED_VPORT);

	qm_info->qm_pq_params[i].tc_id = PURE_LB_TC;

	qm_info->qm_pq_params[i].wrr_group = 1;

	i++;

	qm_info->pure_lb_pq = curr_queue;

	qm_info->qm_pq_params[curr_queue].vport_id =

	    (u8) RESC_START(p_hwfn, QED_VPORT);

	qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC;

	qm_info->qm_pq_params[curr_queue].wrr_group = 1;

	curr_queue++;



	qm_info->offload_pq = 0;

	/* Then init per-VF PQs */

	vf_offset = curr_queue;

	for (i = 0; i < num_vfs; i++) {

		/* First vport is used by the PF */

		qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1;

		qm_info->qm_pq_params[curr_queue].tc_id =

		    p_hwfn->hw_info.non_offload_tc;

		qm_info->qm_pq_params[curr_queue].wrr_group = 1;

		curr_queue++;

	}



	qm_info->vf_queues_offset = vf_offset;

	qm_info->num_pqs = num_pqs;

	qm_info->num_vports = num_vports;
@@ -220,6 +246,7 @@ static int qed_init_qm_info(struct qed_hwfn *p_hwfn) 


	qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ);



	qm_info->num_vf_pqs = num_vfs;

	qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT);



	for (i = 0; i < qm_info->num_vports; i++)
@@ -244,6 +271,9 @@ int qed_resc_alloc(struct qed_dev *cdev) 
	struct qed_eq *p_eq;

	int i, rc = 0;



	if (IS_VF(cdev))

		return rc;



	cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL);

	if (!cdev->fw_data)

		return -ENOMEM;
@@ -364,6 +394,9 @@ void qed_resc_setup(struct qed_dev *cdev) 
{

	int i;



	if (IS_VF(cdev))

		return;



	for_each_hwfn(cdev, i) {

		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];
@@ -508,7 +541,9 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 
	struct qed_qm_info *qm_info = &p_hwfn->qm_info;

	struct qed_qm_common_rt_init_params params;

	struct qed_dev *cdev = p_hwfn->cdev;

	u32 concrete_fid;

	int rc = 0;

	u8 vf_id;



	qed_init_cau_rt_data(cdev);
@@ -558,6 +593,14 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 
	qed_wr(p_hwfn, p_ptt, 0x20b4,

	       qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10);



	for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) {

		concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id);

		qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid);

		qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1);

	}

	/* pretend to original PF */

	qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id);



	return rc;

}
@@ -698,13 +741,20 @@ int qed_hw_init(struct qed_dev *cdev, 
	u32 load_code, param;

	int rc, mfw_rc, i;



	if (IS_PF(cdev)) {

		rc = qed_init_fw_data(cdev, bin_fw_data);

		if (rc != 0)

			return rc;

	}



	for_each_hwfn(cdev, i) {

		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];



		if (IS_VF(cdev)) {

			p_hwfn->b_int_enabled = 1;

			continue;

		}



		/* Enable DMAE in PXP */

		rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true);
@@ -829,6 +879,11 @@ int qed_hw_stop(struct qed_dev *cdev) 


		DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n");



		if (IS_VF(cdev)) {

			/* To be implemented in a later patch */

			continue;

		}



		/* mark the hw as uninitialized... */

		p_hwfn->hw_init_done = false;
@@ -860,15 +915,16 @@ int qed_hw_stop(struct qed_dev *cdev) 
		usleep_range(1000, 2000);

	}



	if (IS_PF(cdev)) {

		/* Disable DMAE in PXP - in CMT, this should only be done for

		 * first hw-function, and only after all transactions have

		 * stopped for all active hw-functions.

		 */

		t_rc = qed_change_pci_hwfn(&cdev->hwfns[0],

				   cdev->hwfns[0].p_main_ptt,

				   false);

					   cdev->hwfns[0].p_main_ptt, false);

		if (t_rc != 0)

			rc = t_rc;

	}



	return rc;

}
@@ -932,6 +988,11 @@ int qed_hw_reset(struct qed_dev *cdev) 
	for_each_hwfn(cdev, i) {

		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];



		if (IS_VF(cdev)) {

			/* Will be implemented in a later patch */

			continue;

		}



		DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n");



		/* Check for incorrect states */
@@ -1027,11 +1088,10 @@ static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 
static void qed_hw_get_resc(struct qed_hwfn *p_hwfn)

{

	u32 *resc_start = p_hwfn->hw_info.resc_start;

	u8 num_funcs = p_hwfn->num_funcs_on_engine;

	u32 *resc_num = p_hwfn->hw_info.resc_num;

	struct qed_sb_cnt_info sb_cnt_info;

	int num_funcs, i;



	num_funcs = MAX_NUM_PFS_BB;

	int i;



	memset(&sb_cnt_info, 0, sizeof(sb_cnt_info));

	qed_int_get_num_sbs(p_hwfn, &sb_cnt_info);
@@ -1238,6 +1298,51 @@ static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, 
	return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt);

}



static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)

{

	u32 reg_function_hide, tmp, eng_mask;

	u8 num_funcs;



	num_funcs = MAX_NUM_PFS_BB;



	/* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values

	 * in the other bits are selected.

	 * Bits 1-15 are for functions 1-15, respectively, and their value is

	 * '0' only for enabled functions (function 0 always exists and

	 * enabled).

	 * In case of CMT, only the "even" functions are enabled, and thus the

	 * number of functions for both hwfns is learnt from the same bits.

	 */

	reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE);



	if (reg_function_hide & 0x1) {

		if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) {

			num_funcs = 0;

			eng_mask = 0xaaaa;

		} else {

			num_funcs = 1;

			eng_mask = 0x5554;

		}



		/* Get the number of the enabled functions on the engine */

		tmp = (reg_function_hide ^ 0xffffffff) & eng_mask;

		while (tmp) {

			if (tmp & 0x1)

				num_funcs++;

			tmp >>= 0x1;

		}

	}



	p_hwfn->num_funcs_on_engine = num_funcs;



	DP_VERBOSE(p_hwfn,

		   NETIF_MSG_PROBE,

		   "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n",

		   p_hwfn->rel_pf_id,

		   p_hwfn->abs_pf_id,

		   p_hwfn->num_funcs_on_engine);

}



static int

qed_get_hw_info(struct qed_hwfn *p_hwfn,

		struct qed_ptt *p_ptt,
@@ -1296,6 +1401,8 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn, 
		p_hwfn->hw_info.personality = protocol;

	}



	qed_get_num_funcs(p_hwfn, p_ptt);



	qed_hw_get_resc(p_hwfn);



	return rc;
@@ -1361,6 +1468,9 @@ static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 
	p_hwfn->regview = p_regview;

	p_hwfn->doorbells = p_doorbells;



	if (IS_VF(p_hwfn->cdev))

		return qed_vf_hw_prepare(p_hwfn);



	/* Validate that chip access is feasible */

	if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {

		DP_ERR(p_hwfn,
@@ -1428,6 +1538,7 @@ int qed_hw_prepare(struct qed_dev *cdev, 
	int rc;



	/* Store the precompiled init data ptrs */

	if (IS_PF(cdev))

		qed_init_iro_array(cdev);



	/* Initialize the first hwfn - will learn number of hwfns */
@@ -1460,11 +1571,13 @@ int qed_hw_prepare(struct qed_dev *cdev, 
		 * initiliazed hwfn 0.

		 */

		if (rc) {

			if (IS_PF(cdev)) {

				qed_init_free(p_hwfn);

				qed_mcp_free(p_hwfn);

				qed_hw_hwfn_free(p_hwfn);

			}

		}

	}



	return rc;

}
@@ -1476,6 +1589,11 @@ void qed_hw_remove(struct qed_dev *cdev) 
	for_each_hwfn(cdev, i) {

		struct qed_hwfn *p_hwfn = &cdev->hwfns[i];



		if (IS_VF(cdev)) {

			/* Will be implemented in a later patch */

			continue;

		}



		qed_init_free(p_hwfn);

		qed_hw_hwfn_free(p_hwfn);

		qed_mcp_free(p_hwfn);