Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 14054fb1 authored by Grygorii Strashko's avatar Grygorii Strashko Committed by Tony Lindgren
Browse files

ARM: dts: am4372: fix clock source for arm twd and global timers 



ARM TWD and Global timer are clocked by PERIPHCLK which is MPU_CLK/2.
But now they are clocked by dpll_mpu_m2_ck == MPU_CLK and, as result.
Timekeeping core misbehaves. For example, execution of command
"sleep 5" will take 10 sec instead of 5.

Hence, fix it by adding mpu_periphclk ("fixed-factor-clock") and use
it for clocking ARM TWD and Global timer (same way as on OMAP4).

Cc: Tony Lindgren <tony@atomide.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Fixes:commit 8cbd4c2f ("arm: boot: dts: am4372: add ARM timers and SCU nodes")
Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: default avatarFelipe Balbi <balbi@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent fc827928

arch/arm/boot/dts/am4372.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -74,7 +74,7 @@ 
		reg = <0x48240200 0x100>;

		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		clocks = <&dpll_mpu_m2_ck>;

		clocks = <&mpu_periphclk>;

	};



	local_timer: timer@48240600 {
@@ -82,7 +82,7 @@ 
		reg = <0x48240600 0x100>;

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-parent = <&gic>;

		clocks = <&dpll_mpu_m2_ck>;

		clocks = <&mpu_periphclk>;

	};



	l2-cache-controller@48242000 {

arch/arm/boot/dts/am43xx-clocks.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -259,6 +259,14 @@ 
		ti,invert-autoidle-bit;

	};



	mpu_periphclk: mpu_periphclk {

		#clock-cells = <0>;

		compatible = "fixed-factor-clock";

		clocks = <&dpll_mpu_m2_ck>;

		clock-mult = <1>;

		clock-div = <2>;

	};



	dpll_ddr_ck: dpll_ddr_ck {

		#clock-cells = <0>;

		compatible = "ti,am3-dpll-clock";