Loading arch/tile/include/asm/system.h +4 −1 Original line number Diff line number Diff line Loading @@ -89,6 +89,10 @@ #define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */ #endif #if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() int __mb_incoherent(void); /* Helper routine for mb_incoherent(). */ #endif /* Fence to guarantee visibility of stores to incoherent memory. */ static inline void mb_incoherent(void) Loading @@ -97,7 +101,6 @@ mb_incoherent(void) #if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() { int __mb_incoherent(void); #if CHIP_HAS_TILE_WRITE_PENDING() const unsigned long WRITE_TIMEOUT_CYCLES = 400; unsigned long start = get_cycles_low(); Loading arch/tile/lib/exports.c +3 −0 Original line number Diff line number Diff line Loading @@ -45,6 +45,9 @@ EXPORT_SYMBOL(__copy_from_user_zeroing); EXPORT_SYMBOL(__copy_in_user_inatomic); #endif /* arch/tile/lib/mb_incoherent.S */ EXPORT_SYMBOL(__mb_incoherent); /* hypervisor glue */ #include <hv/hypervisor.h> EXPORT_SYMBOL(hv_dev_open); Loading Loading
arch/tile/include/asm/system.h +4 −1 Original line number Diff line number Diff line Loading @@ -89,6 +89,10 @@ #define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */ #endif #if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() int __mb_incoherent(void); /* Helper routine for mb_incoherent(). */ #endif /* Fence to guarantee visibility of stores to incoherent memory. */ static inline void mb_incoherent(void) Loading @@ -97,7 +101,6 @@ mb_incoherent(void) #if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() { int __mb_incoherent(void); #if CHIP_HAS_TILE_WRITE_PENDING() const unsigned long WRITE_TIMEOUT_CYCLES = 400; unsigned long start = get_cycles_low(); Loading
arch/tile/lib/exports.c +3 −0 Original line number Diff line number Diff line Loading @@ -45,6 +45,9 @@ EXPORT_SYMBOL(__copy_from_user_zeroing); EXPORT_SYMBOL(__copy_in_user_inatomic); #endif /* arch/tile/lib/mb_incoherent.S */ EXPORT_SYMBOL(__mb_incoherent); /* hypervisor glue */ #include <hv/hypervisor.h> EXPORT_SYMBOL(hv_dev_open); Loading