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Commit 13c76ad8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 mm updates from Ingo Molnar:
 "The main changes in this cycle were:

   - Enable full ASLR randomization for 32-bit programs (Hector
     Marco-Gisbert)

   - Add initial minimal INVPCI support, to flush global mappings (Andy
     Lutomirski)

   - Add KASAN enhancements (Andrey Ryabinin)

   - Fix mmiotrace for huge pages (Karol Herbst)

   - ... misc cleanups and small enhancements"

* 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mm/32: Enable full randomization on i386 and X86_32
  x86/mm/kmmio: Fix mmiotrace for hugepages
  x86/mm: Avoid premature success when changing page attributes
  x86/mm/ptdump: Remove paravirt_enabled()
  x86/mm: Fix INVPCID asm constraint
  x86/dmi: Switch dmi_remap() from ioremap() [uncached] to ioremap_cache()
  x86/mm: If INVPCID is available, use it to flush global mappings
  x86/mm: Add a 'noinvpcid' boot option to turn off INVPCID
  x86/mm: Add INVPCID helpers
  x86/kasan: Write protect kasan zero shadow
  x86/kasan: Clear kasan_zero_page after TLB flush
  x86/mm/numa: Check for failures in numa_clear_kernel_node_hotplug()
  x86/mm/numa: Clean up numa_clear_kernel_node_hotplug()
  x86/mm: Make kmap_prot into a #define
  x86/mm/32: Set NX in __supported_pte_mask before enabling paging
  x86/mm: Streamline and restore probe_memory_block_size()
parents 9cf8d636 8b8addf8

Documentation/kernel-parameters.txt

+2 −0
Original line number Diff line number Diff line
@@ -2566,6 +2566,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 


	nointroute	[IA-64]



	noinvpcid	[X86] Disable the INVPCID cpu feature.



	nojitter	[IA-64] Disables jitter checking for ITC timers.



	no-kvmclock	[X86,KVM] Disable paravirtualized KVM clock driver

arch/x86/include/asm/dmi.h

+1 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ static __always_inline __init void *dmi_alloc(unsigned len) 
/* Use early IO mappings for DMI because it's initialized early */

#define dmi_early_remap		early_ioremap

#define dmi_early_unmap		early_iounmap

#define dmi_remap		ioremap

#define dmi_remap		ioremap_cache

#define dmi_unmap		iounmap



#endif /* _ASM_X86_DMI_H */

arch/x86/include/asm/fixmap.h

+1 −1
Original line number Diff line number Diff line
@@ -138,7 +138,7 @@ extern void reserve_top_address(unsigned long reserve); 
extern int fixmaps_set;



extern pte_t *kmap_pte;

extern pgprot_t kmap_prot;

#define kmap_prot PAGE_KERNEL

extern pte_t *pkmap_page_table;



void __native_set_fixmap(enum fixed_addresses idx, pte_t pte);

arch/x86/include/asm/tlbflush.h

+57 −0
Original line number Diff line number Diff line
@@ -8,6 +8,54 @@ 
#include <asm/cpufeature.h>

#include <asm/special_insns.h>



static inline void __invpcid(unsigned long pcid, unsigned long addr,

			     unsigned long type)

{

	struct { u64 d[2]; } desc = { { pcid, addr } };



	/*

	 * The memory clobber is because the whole point is to invalidate

	 * stale TLB entries and, especially if we're flushing global

	 * mappings, we don't want the compiler to reorder any subsequent

	 * memory accesses before the TLB flush.

	 *

	 * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and

	 * invpcid (%rcx), %rax in long mode.

	 */

	asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"

		      : : "m" (desc), "a" (type), "c" (&desc) : "memory");

}



#define INVPCID_TYPE_INDIV_ADDR		0

#define INVPCID_TYPE_SINGLE_CTXT	1

#define INVPCID_TYPE_ALL_INCL_GLOBAL	2

#define INVPCID_TYPE_ALL_NON_GLOBAL	3



/* Flush all mappings for a given pcid and addr, not including globals. */

static inline void invpcid_flush_one(unsigned long pcid,

				     unsigned long addr)

{

	__invpcid(pcid, addr, INVPCID_TYPE_INDIV_ADDR);

}



/* Flush all mappings for a given PCID, not including globals. */

static inline void invpcid_flush_single_context(unsigned long pcid)

{

	__invpcid(pcid, 0, INVPCID_TYPE_SINGLE_CTXT);

}



/* Flush all mappings, including globals, for all PCIDs. */

static inline void invpcid_flush_all(void)

{

	__invpcid(0, 0, INVPCID_TYPE_ALL_INCL_GLOBAL);

}



/* Flush all mappings for all PCIDs except globals. */

static inline void invpcid_flush_all_nonglobals(void)

{

	__invpcid(0, 0, INVPCID_TYPE_ALL_NON_GLOBAL);

}



#ifdef CONFIG_PARAVIRT

#include <asm/paravirt.h>

#else
@@ -105,6 +153,15 @@ static inline void __native_flush_tlb_global(void) 
{

	unsigned long flags;



	if (static_cpu_has(X86_FEATURE_INVPCID)) {

		/*

		 * Using INVPCID is considerably faster than a pair of writes

		 * to CR4 sandwiched inside an IRQ flag save/restore.

		 */

		invpcid_flush_all();

		return;

	}



	/*

	 * Read-modify-write to CR4 - protect it from preemption and

	 * from interrupts. (Use the raw variant because this code can

arch/x86/kernel/cpu/common.c

+16 −0
Original line number Diff line number Diff line
@@ -162,6 +162,22 @@ static int __init x86_mpx_setup(char *s) 
}

__setup("nompx", x86_mpx_setup);



static int __init x86_noinvpcid_setup(char *s)

{

	/* noinvpcid doesn't accept parameters */

	if (s)

		return -EINVAL;



	/* do not emit a message if the feature is not present */

	if (!boot_cpu_has(X86_FEATURE_INVPCID))

		return 0;



	setup_clear_cpu_cap(X86_FEATURE_INVPCID);

	pr_info("noinvpcid: INVPCID feature disabled\n");

	return 0;

}

early_param("noinvpcid", x86_noinvpcid_setup);



#ifdef CONFIG_X86_32

static int cachesize_override = -1;

static int disable_x86_serial_nr = 1;