Merge "disp: msm: modify stage for dim layer during atomic set" (132f27ff) · Commits · e / devices / android_kernel_fairphone_FP4

msm/sde/sde_crtc.c

+49 −9

Original line number	Diff line number	Diff line
		@@ -2441,16 +2441,17 @@ static void _sde_crtc_clear_dim_layers_v1(struct sde_crtc_state *cstate)
		* @cstate: Pointer to sde crtc state
		* @user_ptr: User ptr for sde_drm_dim_layer_v1 struct
		*/
		static void _sde_crtc_set_dim_layer_v1(struct sde_crtc_state *cstate,
		void __user *usr_ptr)
		static void _sde_crtc_set_dim_layer_v1(struct drm_crtc *crtc,
		struct sde_crtc_state cstate, void __user usr_ptr)
		{
		struct sde_drm_dim_layer_v1 dim_layer_v1;
		struct sde_drm_dim_layer_cfg *user_cfg;
		struct sde_hw_dim_layer *dim_layer;
		u32 count, i;
		struct sde_kms *kms;

		if (!cstate) {
		SDE_ERROR("invalid cstate\n");
		if (!crtc \|\| !cstate) {
		SDE_ERROR("invalid crtc or cstate\n");
		return;
		}
		dim_layer = cstate->dim_layer;
		@@ -2462,6 +2463,12 @@ static void _sde_crtc_set_dim_layer_v1(struct sde_crtc_state *cstate,
		return;
		}

		kms = _sde_crtc_get_kms(crtc);
		if (!kms \|\| !kms->catalog) {
		SDE_ERROR("invalid kms\n");
		return;
		}

		if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
		SDE_ERROR("failed to copy dim_layer data\n");
		return;
		@@ -2479,7 +2486,9 @@ static void _sde_crtc_set_dim_layer_v1(struct sde_crtc_state *cstate,
		user_cfg = &dim_layer_v1.layer_cfg[i];

		dim_layer[i].flags = user_cfg->flags;
		dim_layer[i].stage = user_cfg->stage + SDE_STAGE_0;
		dim_layer[i].stage = (kms->catalog->has_base_layer) ?
		user_cfg->stage : user_cfg->stage +
		SDE_STAGE_0;

		dim_layer[i].rect.x = user_cfg->rect.x1;
		dim_layer[i].rect.y = user_cfg->rect.y1;
		@@ -4236,9 +4245,12 @@ static int _sde_crtc_check_secure_blend_config(struct drm_crtc *crtc,
		int sec_stage = cnt ? pstates[0].sde_pstate->stage :
		cstate->dim_layer[0].stage;

		if (!sde_kms->catalog->has_base_layer)
		sec_stage -= SDE_STAGE_0;

		if ((!cnt && !cstate->num_dim_layers) \|\|
		(sde_kms->catalog->sui_supported_blendstage
		!= (sec_stage - SDE_STAGE_0))) {
		!= sec_stage)) {
		SDE_ERROR(
		"crtc%d: empty cnt%d/dim%d or bad stage%d\n",
		DRMID(crtc), cnt,
		@@ -4392,10 +4404,18 @@ static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
		const struct drm_plane_state *pstate;
		const struct drm_plane_state *pipe_staged[SSPP_MAX];
		int rc = 0, multirect_count = 0, i, mixer_width, mixer_height;
		int inc_sde_stage = 0;
		struct sde_kms *kms;

		sde_crtc = to_sde_crtc(crtc);
		cstate = to_sde_crtc_state(state);

		kms = _sde_crtc_get_kms(crtc);
		if (!kms \|\| !kms->catalog) {
		SDE_ERROR("invalid kms\n");
		return -EINVAL;
		}

		memset(pipe_staged, 0, sizeof(pipe_staged));

		mixer_width = sde_crtc_get_mixer_width(sde_crtc, cstate, mode);
		@@ -4421,10 +4441,13 @@ static int _sde_crtc_check_get_pstates(struct drm_crtc *crtc,
		pstates[*cnt].sde_pstate, PLANE_PROP_ZPOS);
		pstates[*cnt].pipe_id = sde_plane_pipe(plane);

		if (!kms->catalog->has_base_layer)
		inc_sde_stage = SDE_STAGE_0;

		/* check dim layer stage with every plane */
		for (i = 0; i < cstate->num_dim_layers; i++) {
		if (cstate->dim_layer[i].stage ==
		(pstates[*cnt].stage + SDE_STAGE_0)) {
		(pstates[*cnt].stage + inc_sde_stage)) {
		SDE_ERROR(
		"plane:%d/dim_layer:%i-same stage:%d\n",
		plane->base.id, i,
		@@ -4500,6 +4523,16 @@ static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
		{
		int rc = 0, i, z_pos;
		u32 zpos_cnt = 0;
		struct drm_crtc *crtc;
		struct sde_kms *kms;

		crtc = &sde_crtc->base;
		kms = _sde_crtc_get_kms(crtc);

		if (!kms \|\| !kms->catalog) {
		SDE_ERROR("Invalid kms\n");
		return -EINVAL;
		}

		sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);

		@@ -4539,7 +4572,11 @@ static int _sde_crtc_check_zpos(struct drm_crtc_state *state,
		zpos_cnt++;
		}

		if (!kms->catalog->has_base_layer)
		pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
		else
		pstates[i].sde_pstate->stage = z_pos;

		SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos);
		}
		return rc;
		@@ -5022,6 +5059,9 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
		sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",
		catalog->ubwc_bw_calc_version);

		sde_kms_info_add_keyint(info, "use_baselayer_for_stage",
		catalog->has_base_layer);

		msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
		info->data, SDE_KMS_INFO_DATALEN(info), CRTC_PROP_INFO);

		@@ -5114,7 +5154,7 @@ static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
		_sde_crtc_set_input_fence_timeout(cstate);
		break;
		case CRTC_PROP_DIM_LAYER_V1:
		_sde_crtc_set_dim_layer_v1(cstate,
		_sde_crtc_set_dim_layer_v1(crtc, cstate,
		(void __user *)(uintptr_t)val);
		break;
		case CRTC_PROP_ROI_V1:

msm/sde/sde_hw_catalog.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -186,6 +186,7 @@ enum sde_prop {
		PIPE_ORDER_VERSION,
		SEC_SID_MASK,
		SDE_LIMITS,
		BASE_LAYER,
		SDE_PROP_MAX,
		};

		@@ -489,6 +490,7 @@ static struct sde_prop_type sde_prop[] = {
		PROP_TYPE_U32},
		{SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY},
		{SDE_LIMITS, "qcom,sde-limits", false, PROP_TYPE_NODE},
		{BASE_LAYER, "qcom,sde-mixer-stage-base-layer", false, PROP_TYPE_BOOL},
		};

		static struct sde_prop_type sde_perf_prop[] = {
		@@ -3418,6 +3420,7 @@ static int sde_top_parse_dt(struct device_node np, struct sde_mdss_cfg cfg)
		cfg->has_idle_pc = PROP_VALUE_ACCESS(prop_value, IDLE_PC, 0);
		cfg->pipe_order_type = PROP_VALUE_ACCESS(prop_value,
		PIPE_ORDER_VERSION, 0);
		cfg->has_base_layer = PROP_VALUE_ACCESS(prop_value, BASE_LAYER, 0);

		rc = sde_limit_parse_dt(np, cfg);
		if (rc)

msm/sde/sde_hw_catalog.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -1275,6 +1275,7 @@ struct sde_limit_cfg {
		* @has_qos_fl_nocalc flag to indicate QoS fill level needs no calculation
		* @update_tcsr_disp_glitch flag to enable HW workaround to avoid spurious
		* transactions during suspend
		* @has_base_layer Supports staging layer as base layer
		* @sc_cfg: system cache configuration
		* @uidle_cfg Settings for uidle feature
		* @sui_misr_supported indicate if secure-ui-misr is supported
		@@ -1336,6 +1337,7 @@ struct sde_mdss_cfg {
		bool has_decimation;
		bool has_qos_fl_nocalc;
		bool update_tcsr_disp_glitch;
		bool has_base_layer;

		struct sde_sc_cfg sc_cfg;

msm/sde/sde_hw_ctl.c

+4 −2

Original line number	Diff line number	Diff line
		@@ -790,8 +790,6 @@ static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
		else
		pipes_per_stage = 1;

		mixercfg = CTL_MIXER_BORDER_OUT; /* always set BORDER_OUT */

		if (!stage_cfg)
		goto exit;

		@@ -898,6 +896,10 @@ static void sde_hw_ctl_setup_blendstage(struct sde_hw_ctl *ctx,
		}

		exit:
		if ((!mixercfg && !mixercfg_ext && !mixercfg_ext2 && !mixercfg_ext3) \|\|
		(stage_cfg && !stage_cfg->stage[0][0]))
		mixercfg \|= CTL_MIXER_BORDER_OUT;

		SDE_REG_WRITE(c, CTL_LAYER(lm), mixercfg);
		SDE_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext);
		SDE_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2);

msm/sde/sde_hw_lm.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -196,6 +196,9 @@ static void sde_hw_lm_setup_dim_layer(struct sde_hw_mixer *ctx,
		int stage_off;
		u32 val = 0, alpha = 0;

		if (dim_layer->stage == SDE_STAGE_BASE)
		return;

		stage_off = _stage_offset(ctx, dim_layer->stage);
		if (stage_off < 0) {
		SDE_ERROR("invalid stage_off:%d for dim layer\n", stage_off);