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Commit 131b17d4 authored by Bryan Wu's avatar Bryan Wu Committed by Linus Torvalds
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spi: initial BF54x SPI support 



Initial BF54x SPI support

 - support BF54x SPI0
 - clean up some code (whitespace etc)
 - will support multiports in the future
 - start using portmux calls

Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
Signed-off-by: default avatarDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent c24b2602

drivers/spi/spi_bfin5xx.c

+69 −70
Original line number Diff line number Diff line 
/*

 * File:	drivers/spi/bfin5xx_spi.c

 * Based on:     N/A

 * Author:       Luke Yang (Analog Devices Inc.)

 * Maintainer:

 *		Bryan Wu <bryan.wu@analog.com>

 * Original Author:

 *		Luke Yang (Analog Devices Inc.)

 *

 * Created:	March. 10th 2006

 * Description:  SPI controller driver for Blackfin 5xx

 * Description:	SPI controller driver for Blackfin BF5xx

 * Bugs:	Enter bugs at http://blackfin.uclinux.org/

 *

 * Modified:

 *	March 10, 2006  bfin5xx_spi.c Created. (Luke Yang)

 *      August 7, 2006  added full duplex mode (Axel Weiss & Luke Yang)

 *      July  17, 2007  add support for BF54x SPI0 controller (Bryan Wu)

 *

 * Copyright 2004-2006 Analog Devices Inc.

 * Copyright 2004-2007 Analog Devices Inc.

 *

 * This program is free software ;  you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -31,27 +34,27 @@ 


#include <linux/init.h>

#include <linux/module.h>

#include <linux/delay.h>

#include <linux/device.h>

#include <linux/io.h>

#include <linux/ioport.h>

#include <linux/irq.h>

#include <linux/errno.h>

#include <linux/interrupt.h>

#include <linux/platform_device.h>

#include <linux/dma-mapping.h>

#include <linux/spi/spi.h>

#include <linux/workqueue.h>

#include <linux/delay.h>



#include <asm/io.h>

#include <asm/irq.h>

#include <asm/delay.h>

#include <asm/dma.h>



#include <asm/portmux.h>

#include <asm/bfin5xx_spi.h>



MODULE_AUTHOR("Luke Yang");

MODULE_DESCRIPTION("Blackfin 5xx SPI Contoller");

MODULE_AUTHOR("Bryan Wu, Luke Yang");

MODULE_DESCRIPTION("Blackfin BF5xx SPI Contoller Driver");

MODULE_LICENSE("GPL");



#define DRV_NAME	"bfin-spi-master"

#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)



#define DEFINE_SPI_REG(reg, off) \
@@ -124,6 +127,7 @@ struct chip_data { 
	u16 flag;



	u8 chip_select_num;

	u8 chip_select_requested;

	u8 n_bytes;

	u8 width;		/* 0 or 1 */

	u8 enable_dma;
@@ -188,53 +192,37 @@ static void restore_state(struct driver_data *drv_data) 
	bfin_spi_disable(drv_data);

	dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");



#if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)

	if (!chip->chip_select_requested) {



		dev_dbg(&drv_data->pdev->dev,

		"chip select number is %d\n", chip->chip_select_num);



		switch (chip->chip_select_num) {

		case 1:

		bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00);

		SSYNC();

			peripheral_request(P_SPI0_SSEL1, DRV_NAME);

			break;



		case 2:

			peripheral_request(P_SPI0_SSEL2, DRV_NAME);

			break;

		case 3:

		bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI);

		SSYNC();

		bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);

		SSYNC();

			peripheral_request(P_SPI0_SSEL3, DRV_NAME);

			break;



		case 4:

		bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI);

		SSYNC();

		bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840);

		SSYNC();

			peripheral_request(P_SPI0_SSEL4, DRV_NAME);

			break;



		case 5:

		bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI);

		SSYNC();

		bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820);

		SSYNC();

			peripheral_request(P_SPI0_SSEL5, DRV_NAME);

			break;



		case 6:

		bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI);

		SSYNC();

		bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810);

		SSYNC();

			peripheral_request(P_SPI0_SSEL6, DRV_NAME);

			break;



		case 7:

		bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI);

		SSYNC();

		bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800);

		SSYNC();

			peripheral_request(P_SPI0_SSEL7, DRV_NAME);

			break;

		}

#endif



		chip->chip_select_requested = 1;

	}



	/* Load the registers */

	write_CTRL(chip->ctl_reg);
@@ -700,8 +688,8 @@ static void pump_transfers(unsigned long data) 
	drv_data->write = drv_data->tx ? chip->write : null_writer;

	drv_data->read = drv_data->rx ? chip->read : null_reader;

	drv_data->duplex = chip->duplex ? chip->duplex : null_writer;

	dev_dbg(&drv_data->pdev->dev,

		"transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",

	dev_dbg(&drv_data->pdev->dev, "transfer: ",

		"drv_data->write is %p, chip->write is %p, null_wr is %p\n",

		drv_data->write, chip->write, null_writer);



	/* speed and width has been set on per message */
@@ -881,9 +869,11 @@ static void pump_transfers(unsigned long data) 
/* pop a msg from queue and kick off real transfer */

static void pump_messages(struct work_struct *work)

{

	struct driver_data *drv_data = container_of(work, struct driver_data, pump_messages);

	struct driver_data *drv_data;

	unsigned long flags;



	drv_data = container_of(work, struct driver_data, pump_messages);



	/* Lock queue and check for queue work */

	spin_lock_irqsave(&drv_data->lock, flags);

	if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
@@ -1193,6 +1183,15 @@ static int __init bfin5xx_spi_probe(struct platform_device *pdev) 
		dev_err(&pdev->dev, "can not alloc spi_master\n");

		return -ENOMEM;

	}



	if (peripheral_request(P_SPI0_SCK, DRV_NAME) ||

		 peripheral_request(P_SPI0_MISO, DRV_NAME) ||

		 peripheral_request(P_SPI0_MOSI, DRV_NAME)) {



		dev_err(&pdev->dev, ": Requesting Peripherals failed\n");

		goto out_error_queue_alloc;

	}



	drv_data = spi_master_get_devdata(master);

	drv_data->master = master;

	drv_data->master_info = platform_info;

include/asm-blackfin/mach-bf548/defBF54x_base.h

+17 −0
Original line number Diff line number Diff line
@@ -1644,8 +1644,25 @@ 
#define                   RESTART  0x20       /* Work Unit Transitions */

#define                    DI_SEL  0x40       /* Data Interrupt Timing Select */

#define                     DI_EN  0x80       /* Data Interrupt Enable */



#define                    NDSIZE  0xf00      /* Flex Descriptor Size */

#define                  NDSIZE_0 0x0000      /* Next Descriptor Size = 0 (Stop/Autobuffer) */

#define                  NDSIZE_1 0x0100      /* Next Descriptor Size = 1 */

#define                  NDSIZE_2 0x0200      /* Next Descriptor Size = 2 */

#define                  NDSIZE_3 0x0300      /* Next Descriptor Size = 3 */

#define                  NDSIZE_4 0x0400      /* Next Descriptor Size = 4 */

#define                  NDSIZE_5 0x0500      /* Next Descriptor Size = 5 */

#define                  NDSIZE_6 0x0600      /* Next Descriptor Size = 6 */

#define                  NDSIZE_7 0x0700      /* Next Descriptor Size = 7 */

#define                  NDSIZE_8 0x0800      /* Next Descriptor Size = 8 */

#define                  NDSIZE_9 0x0900      /* Next Descriptor Size = 9 */



#define                   DMAFLOW  0xf000     /* Next Operation */

#define              DMAFLOW_STOP  0x0000     /* Stop Mode */

#define              DMAFLOW_AUTO  0x1000     /* Autobuffer Mode */

#define             DMAFLOW_ARRAY  0x4000     /* Descriptor Array Mode */

#define             DMAFLOW_SMALL  0x6000     /* Small Model Descriptor List Mode */

#define             DMAFLOW_LARGE  0x7000     /* Large Model Descriptor List Mode */



/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */