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Commit 130f1b8f authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

PCI: Add PCIe Link Capability link speed and width names 



Add standard #defines for the Supported Link Speeds field in the PCIe
Link Capabilities register.

Note that prior to PCIe spec r3.0, these encodings were defined:

    0001b  2.5GT/s Link speed supported
    0010b  5.0GT/s and 2.5GT/s Link speed supported

Starting with spec r3.0, these encodings refer to bits 0 and 1 in the
Supported Link Speeds Vector in the Link Capabilities 2 register, and bits
0 and 1 there mean 2.5 GT/s and 5.0 GT/s, respectively.  Therefore, code
that followed r2.0 and interpreted 0x1 as 2.5GT/s and 0x2 as 5.0GT/s will
continue to work, and we can identify a device using the new encodings
because it will have a non-zero Link Capabilities 2 register.

Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent 1278998f

include/uapi/linux/pci_regs.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -458,6 +458,8 @@ 
#define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */

#define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */

#define PCI_EXP_LNKCAP		12	/* Link Capabilities */

#define PCI_EXP_LNKCAP		12	/* Link Capabilities */

#define  PCI_EXP_LNKCAP_SLS	0x0000000f /* Supported Link Speeds */

#define  PCI_EXP_LNKCAP_SLS	0x0000000f /* Supported Link Speeds */

#define  PCI_EXP_LNKCAP_SLS_2_5GB 0x1	/* LNKCAP2 SLS Vector bit 0 (2.5GT/s) */

#define  PCI_EXP_LNKCAP_SLS_5_0GB 0x2	/* LNKCAP2 SLS Vector bit 1 (5.0GT/s) */

#define  PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */

#define  PCI_EXP_LNKCAP_MLW	0x000003f0 /* Maximum Link Width */

#define  PCI_EXP_LNKCAP_ASPMS	0x00000c00 /* ASPM Support */

#define  PCI_EXP_LNKCAP_ASPMS	0x00000c00 /* ASPM Support */

#define  PCI_EXP_LNKCAP_L0SEL	0x00007000 /* L0s Exit Latency */

#define  PCI_EXP_LNKCAP_L0SEL	0x00007000 /* L0s Exit Latency */