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Commit 12c1f339 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt Committed by Michael Ellerman
Browse files

powerpc/xive: Move definition of ESB bits 



From xive.h to xive-regs.h since it's a HW register definition
and it can be used from assembly

Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 191eccb1

arch/powerpc/include/asm/xive-regs.h

+35 −0
Original line number Diff line number Diff line
@@ -9,6 +9,41 @@ 
#ifndef _ASM_POWERPC_XIVE_REGS_H

#define _ASM_POWERPC_XIVE_REGS_H



/*

 * "magic" Event State Buffer (ESB) MMIO offsets.

 *

 * Each interrupt source has a 2-bit state machine called ESB

 * which can be controlled by MMIO. It's made of 2 bits, P and

 * Q. P indicates that an interrupt is pending (has been sent

 * to a queue and is waiting for an EOI). Q indicates that the

 * interrupt has been triggered while pending.

 *

 * This acts as a coalescing mechanism in order to guarantee

 * that a given interrupt only occurs at most once in a queue.

 *

 * When doing an EOI, the Q bit will indicate if the interrupt

 * needs to be re-triggered.

 *

 * The following offsets into the ESB MMIO allow to read or

 * manipulate the PQ bits. They must be used with an 8-bytes

 * load instruction. They all return the previous state of the

 * interrupt (atomically).

 *

 * Additionally, some ESB pages support doing an EOI via a

 * store at 0 and some ESBs support doing a trigger via a

 * separate trigger page.

 */

#define XIVE_ESB_STORE_EOI	0x400 /* Store */

#define XIVE_ESB_LOAD_EOI	0x000 /* Load */

#define XIVE_ESB_GET		0x800 /* Load */

#define XIVE_ESB_SET_PQ_00	0xc00 /* Load */

#define XIVE_ESB_SET_PQ_01	0xd00 /* Load */

#define XIVE_ESB_SET_PQ_10	0xe00 /* Load */

#define XIVE_ESB_SET_PQ_11	0xf00 /* Load */



#define XIVE_ESB_VAL_P		0x2

#define XIVE_ESB_VAL_Q		0x1



/*

 * Thread Management (aka "TM") registers

 */

arch/powerpc/include/asm/xive.h

+0 −35
Original line number Diff line number Diff line
@@ -72,41 +72,6 @@ struct xive_q { 
	atomic_t		pending_count;

};



/*

 * "magic" Event State Buffer (ESB) MMIO offsets.

 *

 * Each interrupt source has a 2-bit state machine called ESB

 * which can be controlled by MMIO. It's made of 2 bits, P and

 * Q. P indicates that an interrupt is pending (has been sent

 * to a queue and is waiting for an EOI). Q indicates that the

 * interrupt has been triggered while pending.

 *

 * This acts as a coalescing mechanism in order to guarantee

 * that a given interrupt only occurs at most once in a queue.

 *

 * When doing an EOI, the Q bit will indicate if the interrupt

 * needs to be re-triggered.

 *

 * The following offsets into the ESB MMIO allow to read or

 * manipulate the PQ bits. They must be used with an 8-bytes

 * load instruction. They all return the previous state of the

 * interrupt (atomically).

 *

 * Additionally, some ESB pages support doing an EOI via a

 * store at 0 and some ESBs support doing a trigger via a

 * separate trigger page.

 */

#define XIVE_ESB_STORE_EOI	0x400 /* Store */

#define XIVE_ESB_LOAD_EOI	0x000 /* Load */

#define XIVE_ESB_GET		0x800 /* Load */

#define XIVE_ESB_SET_PQ_00	0xc00 /* Load */

#define XIVE_ESB_SET_PQ_01	0xd00 /* Load */

#define XIVE_ESB_SET_PQ_10	0xe00 /* Load */

#define XIVE_ESB_SET_PQ_11	0xf00 /* Load */



#define XIVE_ESB_VAL_P		0x2

#define XIVE_ESB_VAL_Q		0x1



/* Global enable flags for the XIVE support */

extern bool __xive_enabled;