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Commit 12871a0b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'drm-radeon-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 

* 'drm-radeon-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm/radeon/kms/atom: fix PHY init
  drm/radeon/kms: add missing Evergreen texture formats to the CS parser
  drm/radeon/kms: viewport height has to be even
  drm/radeon/kms: remove duplicate reg from r600 safe regs
  drm/radeon/kms: add support for Llano Fusion APUs
  drm/radeon/kms: add llano pci ids
  drm/radeon/kms: fill in asic struct for llano
  drm/radeon/kms: add family ids for llano APUs
  drm/radeon: fix oops in ttm reserve when pageflipping (v2)
  drm/radeon/kms: clean up the radeon kms Kconfig
  drm/radeon/kms: fix thermal sensor reading on juniper
  drm/radeon/kms: add missing case for cayman thermal sensor
  drm/radeon/kms: add blit support for cayman (v2)
  drm/radeon/kms/blit: workaround some hw issues on evergreen+
parents ecff4fcc f3aeceac

drivers/gpu/drm/radeon/Kconfig

+1 −8
Original line number Diff line number Diff line
@@ -28,11 +28,4 @@ config DRM_RADEON_KMS 
	  The kernel will also perform security check on command stream

	  provided by the user, we want to catch and forbid any illegal use

	  of the GPU such as DMA into random system memory or into memory

	  not owned by the process supplying the command stream. This part

	  of the code is still incomplete and this why we propose that patch

	  as a staging driver addition, future security might forbid current

	  experimental userspace to run.



	  This code support the following hardware : R1XX,R2XX,R3XX,R4XX,R5XX

	  (radeon up to X1950). Works is underway to provide support for R6XX,

	  R7XX and newer hardware (radeon from HD2XXX to HD4XXX).
 
	  not owned by the process supplying the command stream.

drivers/gpu/drm/radeon/atombios_crtc.c

+8 −4
Original line number Diff line number Diff line
@@ -1045,7 +1045,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
	uint64_t fb_location;

	uint32_t fb_format, fb_pitch_pixels, tiling_flags;

	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);

	u32 tmp;

	u32 tmp, viewport_w, viewport_h;

	int r;



	/* no fb bound */
@@ -1171,8 +1171,10 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 
	y &= ~1;

	WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,

	       (x << 16) | y);

	viewport_w = crtc->mode.hdisplay;

	viewport_h = (crtc->mode.vdisplay + 1) & ~1;

	WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

	       (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);

	       (viewport_w << 16) | viewport_h);



	/* pageflip setup */

	/* make sure flip is at vb rather than hb */
@@ -1213,7 +1215,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 
	uint64_t fb_location;

	uint32_t fb_format, fb_pitch_pixels, tiling_flags;

	u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;

	u32 tmp;

	u32 tmp, viewport_w, viewport_h;

	int r;



	/* no fb bound */
@@ -1338,8 +1340,10 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 
	y &= ~1;

	WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,

	       (x << 16) | y);

	viewport_w = crtc->mode.hdisplay;

	viewport_h = (crtc->mode.vdisplay + 1) & ~1;

	WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,

	       (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);

	       (viewport_w << 16) | viewport_h);



	/* pageflip setup */

	/* make sure flip is at vb rather than hb */

drivers/gpu/drm/radeon/cayman_blit_shaders.c

+322 −4
Original line number Diff line number Diff line
@@ -39,17 +39,335 @@ 


const u32 cayman_default_state[] =

{

	/* XXX fill in additional blit state */

	0xc0066900,

	0x00000000,

	0x00000060, /* DB_RENDER_CONTROL */

	0x00000000, /* DB_COUNT_CONTROL */

	0x00000000, /* DB_DEPTH_VIEW */

	0x0000002a, /* DB_RENDER_OVERRIDE */

	0x00000000, /* DB_RENDER_OVERRIDE2 */

	0x00000000, /* DB_HTILE_DATA_BASE */



	0xc0026900,

	0x00000316,

	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */

	0x00000010, /*  */

	0x0000000a,

	0x00000000, /* DB_STENCIL_CLEAR */

	0x00000000, /* DB_DEPTH_CLEAR */



	0xc0036900,

	0x0000000f,

	0x00000000, /* DB_DEPTH_INFO */

	0x00000000, /* DB_Z_INFO */

	0x00000000, /* DB_STENCIL_INFO */



	0xc0016900,

	0x00000080,

	0x00000000, /* PA_SC_WINDOW_OFFSET */



	0xc00d6900,

	0x00000083,

	0x0000ffff, /* PA_SC_CLIPRECT_RULE */

	0x00000000, /* PA_SC_CLIPRECT_0_TL */

	0x20002000, /* PA_SC_CLIPRECT_0_BR */

	0x00000000,

	0x20002000,

	0x00000000,

	0x20002000,

	0x00000000,

	0x20002000,

	0xaaaaaaaa, /* PA_SC_EDGERULE */

	0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */

	0x0000000f, /* CB_TARGET_MASK */

	0x0000000f, /* CB_SHADER_MASK */



	0xc0226900,

	0x00000094,

	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */

	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x80000000,

	0x20002000,

	0x00000000, /* PA_SC_VPORT_ZMIN_0 */

	0x3f800000, /* PA_SC_VPORT_ZMAX_0 */



	0xc0016900,

	0x000000d4,

	0x00000000, /* SX_MISC */



	0xc0026900,

	0x000000d9,

	0x00000000, /* CP_RINGID */

	0x00000000, /* CP_VMID */



	0xc0096900,

	0x00000100,

	0x00ffffff, /* VGT_MAX_VTX_INDX */

	0x00000000, /* VGT_MIN_VTX_INDX */

	0x00000000, /* VGT_INDX_OFFSET */

	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */

	0x00000000, /* SX_ALPHA_TEST_CONTROL */

	0x00000000, /* CB_BLEND_RED */

	0x00000000, /* CB_BLEND_GREEN */

	0x00000000, /* CB_BLEND_BLUE */

	0x00000000, /* CB_BLEND_ALPHA */



	0xc0016900,

	0x00000187,

	0x00000100, /* SPI_VS_OUT_ID_0 */



	0xc0026900,

	0x00000191,

	0x00000100, /* SPI_PS_INPUT_CNTL_0 */

	0x00000101, /* SPI_PS_INPUT_CNTL_1 */



	0xc0016900,

	0x000001b1,

	0x00000000, /* SPI_VS_OUT_CONFIG */



	0xc0106900,

	0x000001b3,

	0x20000001, /* SPI_PS_IN_CONTROL_0 */

	0x00000000, /* SPI_PS_IN_CONTROL_1 */

	0x00000000, /* SPI_INTERP_CONTROL_0 */

	0x00000000, /* SPI_INPUT_Z */

	0x00000000, /* SPI_FOG_CNTL */

	0x00100000, /* SPI_BARYC_CNTL */

	0x00000000, /* SPI_PS_IN_CONTROL_2 */

	0x00000000, /* SPI_COMPUTE_INPUT_CNTL */

	0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */

	0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */

	0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */

	0x00000000, /* SPI_GPR_MGMT */

	0x00000000, /* SPI_LDS_MGMT */

	0x00000000, /* SPI_STACK_MGMT */

	0x00000000, /* SPI_WAVE_MGMT_1 */

	0x00000000, /* SPI_WAVE_MGMT_2 */



	0xc0016900,

	0x000001e0,

	0x00000000, /* CB_BLEND0_CONTROL */



	0xc00e6900,

	0x00000200,

	0x00000000, /* DB_DEPTH_CONTROL */

	0x00000000, /* DB_EQAA */

	0x00cc0010, /* CB_COLOR_CONTROL */

	0x00000210, /* DB_SHADER_CONTROL */

	0x00010000, /* PA_CL_CLIP_CNTL */

	0x00000004, /* PA_SU_SC_MODE_CNTL */

	0x00000100, /* PA_CL_VTE_CNTL */

	0x00000000, /* PA_CL_VS_OUT_CNTL */

	0x00000000, /* PA_CL_NANINF_CNTL */

	0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */

	0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */

	0x00000000, /* PA_SU_PRIM_FILTER_CNTL */

	0x00000000, /*  */

	0x00000000, /*  */



	0xc0026900,

	0x00000229,

	0x00000000, /* SQ_PGM_START_FS */

	0x00000000,



	0xc0016900,

	0x0000023b,

	0x00000000, /* SQ_LDS_ALLOC_PS */



	0xc0066900,

	0x00000240,

	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,



	0xc0046900,

	0x00000247,

	0x00000000, /* SQ_GS_VERT_ITEMSIZE */

	0x00000000,

	0x00000000,

	0x00000000,



	0xc0116900,

	0x00000280,

	0x00000000, /* PA_SU_POINT_SIZE */

	0x00000000, /* PA_SU_POINT_MINMAX */

	0x00000008, /* PA_SU_LINE_CNTL */

	0x00000000, /* PA_SC_LINE_STIPPLE */

	0x00000000, /* VGT_OUTPUT_PATH_CNTL */

	0x00000000, /* VGT_HOS_CNTL */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000, /* VGT_GS_MODE */



	0xc0026900,

	0x00000292,

	0x00000000, /* PA_SC_MODE_CNTL_0 */

	0x00000000, /* PA_SC_MODE_CNTL_1 */



	0xc0016900,

	0x000002a1,

	0x00000000, /* VGT_PRIMITIVEID_EN */



	0xc0016900,

	0x000002a5,

	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */



	0xc0026900,

	0x000002a8,

	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */

	0x00000000,



	0xc0026900,

	0x000002ad,

	0x00000000, /* VGT_REUSE_OFF */

	0x00000000,



	0xc0016900,

	0x000002d5,

	0x00000000, /* VGT_SHADER_STAGES_EN */



	0xc0016900,

	0x000002dc,

	0x0000aa00, /* DB_ALPHA_TO_MASK */



	0xc0066900,

	0x000002de,

	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,



	0xc0026900,

	0x000002e5,

	0x00000000, /* VGT_STRMOUT_CONFIG */

	0x00000000,



	0xc01b6900,

	0x000002f5,

	0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */

	0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */

	0x00000000, /* PA_SC_LINE_CNTL */

	0x00000000, /* PA_SC_AA_CONFIG */

	0x00000005, /* PA_SU_VTX_CNTL */

	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */

	0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */

	0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */

	0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */

	0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0x00000000,

	0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */

	0xffffffff,



	0xc0026900,

	0x00000316,

	0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */

	0x00000010, /*  */

};



const u32 cayman_vs[] =

{

	0x00000004,

	0x80400400,

	0x0000a03c,

	0x95000688,

	0x00004000,

	0x15000688,

	0x00000000,

	0x88000000,

	0x04000000,

	0x67961001,

#ifdef __BIG_ENDIAN

	0x00020000,

#else

	0x00000000,

#endif

	0x00000000,

	0x04000000,

	0x67961000,

#ifdef __BIG_ENDIAN

	0x00020008,

#else

	0x00000008,

#endif

	0x00000000,

};



const u32 cayman_ps[] =

{

	0x00000004,

	0xa00c0000,

	0x00000008,

	0x80400000,

	0x00000000,

	0x95000688,

	0x00000000,

	0x88000000,

	0x00380400,

	0x00146b10,

	0x00380000,

	0x20146b10,

	0x00380400,

	0x40146b00,

	0x80380000,

	0x60146b00,

	0x00000010,

	0x000d1000,

	0xb0800000,

	0x00000000,

};



const u32 cayman_ps_size = ARRAY_SIZE(cayman_ps);

const u32 cayman_vs_size = ARRAY_SIZE(cayman_vs);

const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);

drivers/gpu/drm/radeon/cayman_blit_shaders.h

+3 −0
Original line number Diff line number Diff line
@@ -25,8 +25,11 @@ 
#ifndef CAYMAN_BLIT_SHADERS_H

#define CAYMAN_BLIT_SHADERS_H



extern const u32 cayman_ps[];

extern const u32 cayman_vs[];

extern const u32 cayman_default_state[];



extern const u32 cayman_ps_size, cayman_vs_size;

extern const u32 cayman_default_size;



#endif

drivers/gpu/drm/radeon/evergreen.c

+90 −14
Original line number Diff line number Diff line
@@ -88,9 +88,24 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) 
/* get temperature in millidegrees */

int evergreen_get_temp(struct radeon_device *rdev)

{

	u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>

	u32 temp, toffset, actual_temp = 0;



	if (rdev->family == CHIP_JUNIPER) {

		toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>

			TOFFSET_SHIFT;

		temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>

			TS0_ADC_DOUT_SHIFT;



		if (toffset & 0x100)

			actual_temp = temp / 2 - (0x200 - toffset);

		else

			actual_temp = temp / 2 + toffset;



		actual_temp = actual_temp * 1000;



	} else {

		temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>

			ASIC_T_SHIFT;

	u32 actual_temp = 0;



		if (temp & 0x400)

			actual_temp = -256;
@@ -102,7 +117,10 @@ int evergreen_get_temp(struct radeon_device *rdev) 
		} else

			actual_temp = temp & 0xff;



	return (actual_temp * 1000) / 2;

		actual_temp = (actual_temp * 1000) / 2;

	}



	return actual_temp;

}



int sumo_get_temp(struct radeon_device *rdev)
@@ -1415,6 +1433,8 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev, 
	case CHIP_CEDAR:

	case CHIP_REDWOOD:

	case CHIP_PALM:

	case CHIP_SUMO:

	case CHIP_SUMO2:

	case CHIP_TURKS:

	case CHIP_CAICOS:

		force_no_swizzle = false;
@@ -1544,6 +1564,8 @@ static void evergreen_program_channel_remap(struct radeon_device *rdev) 
	case CHIP_REDWOOD:

	case CHIP_CEDAR:

	case CHIP_PALM:

	case CHIP_SUMO:

	case CHIP_SUMO2:

	case CHIP_TURKS:

	case CHIP_CAICOS:

	default:
@@ -1685,6 +1707,54 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
		rdev->config.evergreen.max_hw_contexts = 4;

		rdev->config.evergreen.sq_num_cf_insts = 1;



		rdev->config.evergreen.sc_prim_fifo_size = 0x40;

		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

		break;

	case CHIP_SUMO:

		rdev->config.evergreen.num_ses = 1;

		rdev->config.evergreen.max_pipes = 4;

		rdev->config.evergreen.max_tile_pipes = 2;

		if (rdev->pdev->device == 0x9648)

			rdev->config.evergreen.max_simds = 3;

		else if ((rdev->pdev->device == 0x9647) ||

			 (rdev->pdev->device == 0x964a))

			rdev->config.evergreen.max_simds = 4;

		else

			rdev->config.evergreen.max_simds = 5;

		rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;

		rdev->config.evergreen.max_gprs = 256;

		rdev->config.evergreen.max_threads = 248;

		rdev->config.evergreen.max_gs_threads = 32;

		rdev->config.evergreen.max_stack_entries = 256;

		rdev->config.evergreen.sx_num_of_sets = 4;

		rdev->config.evergreen.sx_max_export_size = 256;

		rdev->config.evergreen.sx_max_export_pos_size = 64;

		rdev->config.evergreen.sx_max_export_smx_size = 192;

		rdev->config.evergreen.max_hw_contexts = 8;

		rdev->config.evergreen.sq_num_cf_insts = 2;



		rdev->config.evergreen.sc_prim_fifo_size = 0x40;

		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;

		break;

	case CHIP_SUMO2:

		rdev->config.evergreen.num_ses = 1;

		rdev->config.evergreen.max_pipes = 4;

		rdev->config.evergreen.max_tile_pipes = 4;

		rdev->config.evergreen.max_simds = 2;

		rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;

		rdev->config.evergreen.max_gprs = 256;

		rdev->config.evergreen.max_threads = 248;

		rdev->config.evergreen.max_gs_threads = 32;

		rdev->config.evergreen.max_stack_entries = 512;

		rdev->config.evergreen.sx_num_of_sets = 4;

		rdev->config.evergreen.sx_max_export_size = 256;

		rdev->config.evergreen.sx_max_export_pos_size = 64;

		rdev->config.evergreen.sx_max_export_smx_size = 192;

		rdev->config.evergreen.max_hw_contexts = 8;

		rdev->config.evergreen.sq_num_cf_insts = 2;



		rdev->config.evergreen.sc_prim_fifo_size = 0x40;

		rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;

		rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
@@ -2039,6 +2109,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	switch (rdev->family) {

	case CHIP_CEDAR:

	case CHIP_PALM:

	case CHIP_SUMO:

	case CHIP_SUMO2:

	case CHIP_CAICOS:

		/* no vertex cache */

		sq_config &= ~VC_ENABLE;
@@ -2060,6 +2132,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	switch (rdev->family) {

	case CHIP_CEDAR:

	case CHIP_PALM:

	case CHIP_SUMO:

	case CHIP_SUMO2:

		ps_thread_count = 96;

		break;

	default:
@@ -2099,6 +2173,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev) 
	switch (rdev->family) {

	case CHIP_CEDAR:

	case CHIP_PALM:

	case CHIP_SUMO:

	case CHIP_SUMO2:

	case CHIP_CAICOS:

		vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);

		break;