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Commit 1220a3e5 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux into drm-next 

Misc fixes for 4.15.

* 'drm-next-4.15' of git://people.freedesktop.org/~agd5f/linux:
  drm/amd/pp: fix dpm randomly failed on Vega10
  drm/amdgpu: set f_mapping on exported DMA-bufs
  drm/amdgpu: Properly allocate VM invalidate eng v2
  drm/amd/amdgpu: if visible VRAM allocation fail, fall back to invisible try again
  drm/amd/amdgpu: Fix wave mask in amdgpu_debugfs_wave_read() (v2)
  drm/amdgpu: make AMDGPU_VA_RESERVED_SIZE 64bit
  drm/amdgpu/gfx9: implement wave VGPR reading
  drm/amdgpu: Add common golden settings for GFX9
  drm/amd/powerplay: fix copy-n-paste error on vddci_buf index
  drm/amdgpu: Fix null pointer issue in amdgpu_cs_wait_any_fence
  drm/amdgpu: Remove check which is not valid for certain VBIOS
parents f150891f 451cc55d

drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c

+0 −6
Original line number Diff line number Diff line
@@ -59,12 +59,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size) 
		return false;

	}



	tmp = bios[0x18] | (bios[0x19] << 8);

	if (bios[tmp + 0x14] != 0x0) {

		DRM_INFO("Not an x86 BIOS ROM\n");

		return false;

	}



	bios_header_start = bios[0x48] | (bios[0x49] << 8);

	if (!bios_header_start) {

		DRM_INFO("Can't locate bios header\n");

drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

+5 −2
Original line number Diff line number Diff line
@@ -1497,8 +1497,11 @@ static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev, 
	memset(wait, 0, sizeof(*wait));

	wait->out.status = (r > 0);

	wait->out.first_signaled = first;

	/* set return value 0 to indicate success */



	if (array[first])

		r = array[first]->error;

	else

		r = 0;



err_free_fence_array:

	for (i = 0; i < fence_count; i++)

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+20 −20
Original line number Diff line number Diff line
@@ -3188,9 +3188,9 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf, 
	pm_pg_lock = (*pos >> 23) & 1;



	if (*pos & (1ULL << 62)) {

		se_bank = (*pos >> 24) & 0x3FF;

		sh_bank = (*pos >> 34) & 0x3FF;

		instance_bank = (*pos >> 44) & 0x3FF;

		se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;

		sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;

		instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;



		if (se_bank == 0x3FF)

			se_bank = 0xFFFFFFFF;
@@ -3264,9 +3264,9 @@ static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf, 
	pm_pg_lock = (*pos >> 23) & 1;



	if (*pos & (1ULL << 62)) {

		se_bank = (*pos >> 24) & 0x3FF;

		sh_bank = (*pos >> 34) & 0x3FF;

		instance_bank = (*pos >> 44) & 0x3FF;

		se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;

		sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;

		instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;



		if (se_bank == 0x3FF)

			se_bank = 0xFFFFFFFF;
@@ -3614,12 +3614,12 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf, 
		return -EINVAL;



	/* decode offset */

	offset = (*pos & 0x7F);

	se = ((*pos >> 7) & 0xFF);

	sh = ((*pos >> 15) & 0xFF);

	cu = ((*pos >> 23) & 0xFF);

	wave = ((*pos >> 31) & 0xFF);

	simd = ((*pos >> 37) & 0xFF);

	offset = (*pos & GENMASK_ULL(6, 0));

	se = (*pos & GENMASK_ULL(14, 7)) >> 7;

	sh = (*pos & GENMASK_ULL(22, 15)) >> 15;

	cu = (*pos & GENMASK_ULL(30, 23)) >> 23;

	wave = (*pos & GENMASK_ULL(36, 31)) >> 31;

	simd = (*pos & GENMASK_ULL(44, 37)) >> 37;



	/* switch to the specific se/sh/cu */

	mutex_lock(&adev->grbm_idx_mutex);
@@ -3664,14 +3664,14 @@ static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf, 
		return -EINVAL;



	/* decode offset */

	offset = (*pos & 0xFFF);       /* in dwords */

	se = ((*pos >> 12) & 0xFF);

	sh = ((*pos >> 20) & 0xFF);

	cu = ((*pos >> 28) & 0xFF);

	wave = ((*pos >> 36) & 0xFF);

	simd = ((*pos >> 44) & 0xFF);

	thread = ((*pos >> 52) & 0xFF);

	bank = ((*pos >> 60) & 1);

	offset = *pos & GENMASK_ULL(11, 0);

	se = (*pos & GENMASK_ULL(19, 12)) >> 12;

	sh = (*pos & GENMASK_ULL(27, 20)) >> 20;

	cu = (*pos & GENMASK_ULL(35, 28)) >> 28;

	wave = (*pos & GENMASK_ULL(43, 36)) >> 36;

	simd = (*pos & GENMASK_ULL(51, 44)) >> 44;

	thread = (*pos & GENMASK_ULL(59, 52)) >> 52;

	bank = (*pos & GENMASK_ULL(61, 60)) >> 60;



	data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);

	if (!data)

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+7 −3
Original line number Diff line number Diff line
@@ -63,6 +63,11 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 
			     flags, NULL, resv, 0, &bo);

	if (r) {

		if (r != -ERESTARTSYS) {

			if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {

				flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;

				goto retry;

			}



			if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {

				initial_domain |= AMDGPU_GEM_DOMAIN_GTT;

				goto retry;
@@ -556,9 +561,8 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 


	if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {

		dev_err(&dev->pdev->dev,

			"va_address 0x%lX is in reserved area 0x%X\n",

			(unsigned long)args->va_address,

			AMDGPU_VA_RESERVED_SIZE);

			"va_address 0x%LX is in reserved area 0x%LX\n",

			args->va_address, AMDGPU_VA_RESERVED_SIZE);

		return -EINVAL;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c

+5 −1
Original line number Diff line number Diff line
@@ -169,10 +169,14 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 
					int flags)

{

	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);

	struct dma_buf *buf;



	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||

	    bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)

		return ERR_PTR(-EPERM);



	return drm_gem_prime_export(dev, gobj, flags);

	buf = drm_gem_prime_export(dev, gobj, flags);

	if (!IS_ERR(buf))

		buf->file->f_mapping = dev->anon_inode->i_mapping;

	return buf;

}