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Commit 11bd04f6 authored by Linus Torvalds's avatar Linus Torvalds
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* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (109 commits)
  PCI: fix coding style issue in pci_save_state()
  PCI: add pci_request_acs
  PCI: fix BUG_ON triggered by logical PCIe root port removal
  PCI: remove ifdefed pci_cleanup_aer_correct_error_status
  PCI: unconditionally clear AER uncorr status register during cleanup
  x86/PCI: claim SR-IOV BARs in pcibios_allocate_resource
  PCI: portdrv: remove redundant definitions
  PCI: portdrv: remove unnecessary struct pcie_port_data
  PCI: portdrv: minor cleanup for pcie_port_device_register
  PCI: portdrv: add missing irq cleanup
  PCI: portdrv: enable device before irq initialization
  PCI: portdrv: cleanup service irqs initialization
  PCI: portdrv: check capabilities first
  PCI: portdrv: move PME capability check
  PCI: portdrv: remove redundant pcie type calculation
  PCI: portdrv: cleanup pcie_device registration
  PCI: portdrv: remove redundant pcie_port_device_probe
  PCI: Always set prefetchable base/limit upper32 registers
  PCI: read-modify-write the pcie device control register when initiating pcie flr
  PCI: show dma_mask bits in /sys
  ...

Fixed up conflicts in:
	arch/x86/kernel/amd_iommu_init.c
	drivers/pci/dmar.c
	drivers/pci/hotplug/acpiphp_glue.c
parents 4e2ccdb0 9e0b5b2c
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+1 −27
Original line number Diff line number Diff line
@@ -37,35 +37,9 @@
#include <xen/interface/xen.h>
#include <xen/interface/version.h>	/* to compile feature.c */
#include <xen/features.h>		/* to comiple xen-netfront.c */
#include <xen/xen.h>
#include <asm/xen/hypercall.h>

/* xen_domain_type is set before executing any C code by early_xen_setup */
enum xen_domain_type {
	XEN_NATIVE,	/* running on bare hardware */
	XEN_PV_DOMAIN,	/* running in a PV domain */
	XEN_HVM_DOMAIN,	/* running in a Xen hvm domain*/
};

#ifdef CONFIG_XEN
extern enum xen_domain_type xen_domain_type;
#else
#define xen_domain_type		XEN_NATIVE
#endif

#define xen_domain()		(xen_domain_type != XEN_NATIVE)
#define xen_pv_domain()		(xen_domain() &&			\
				 xen_domain_type == XEN_PV_DOMAIN)
#define xen_hvm_domain()	(xen_domain() &&			\
				 xen_domain_type == XEN_HVM_DOMAIN)

#ifdef CONFIG_XEN_DOM0
#define xen_initial_domain()	(xen_pv_domain() &&			\
				 (xen_start_info->flags & SIF_INITDOMAIN))
#else
#define xen_initial_domain()	(0)
#endif


#ifdef CONFIG_XEN
extern struct shared_info *HYPERVISOR_shared_info;
extern struct start_info *xen_start_info;
+22 −11
Original line number Diff line number Diff line
@@ -131,6 +131,7 @@ alloc_pci_controller (int seg)
}

struct pci_root_info {
	struct acpi_device *bridge;
	struct pci_controller *controller;
	char *name;
};
@@ -297,9 +298,20 @@ static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
	window->offset = offset;

	if (insert_resource(root, &window->resource)) {
		printk(KERN_ERR "alloc 0x%llx-0x%llx from %s for %s failed\n",
			window->resource.start, window->resource.end,
			root->name, info->name);
		dev_err(&info->bridge->dev,
			"can't allocate host bridge window %pR\n",
			&window->resource);
	} else {
		if (offset)
			dev_info(&info->bridge->dev, "host bridge window %pR "
				 "(PCI address [%#llx-%#llx])\n",
				 &window->resource,
				 window->resource.start - offset,
				 window->resource.end - offset);
		else
			dev_info(&info->bridge->dev,
				 "host bridge window %pR\n",
				 &window->resource);
	}

	return AE_OK;
@@ -319,8 +331,9 @@ pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
		    (res->end - res->start < 16))
			continue;
		if (j >= PCI_BUS_NUM_RESOURCES) {
			printk("Ignoring range [%#llx-%#llx] (%lx)\n",
					res->start, res->end, res->flags);
			dev_warn(&bus->dev,
				 "ignoring host bridge window %pR (no space)\n",
				 res);
			continue;
		}
		bus->resource[j++] = res;
@@ -364,6 +377,7 @@ pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
			goto out3;

		sprintf(name, "PCI Bus %04x:%02x", domain, bus);
		info.bridge = device;
		info.controller = controller;
		info.name = name;
		acpi_walk_resources(device->handle, METHOD_NAME__CRS,
@@ -720,9 +734,6 @@ int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
	return ret;
}

/* It's defined in drivers/pci/pci.c */
extern u8 pci_cache_line_size;

/**
 * set_pci_cacheline_size - determine cacheline size for PCI devices
 *
@@ -731,7 +742,7 @@ extern u8 pci_cache_line_size;
 *
 * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
 */
static void __init set_pci_cacheline_size(void)
static void __init set_pci_dfl_cacheline_size(void)
{
	unsigned long levels, unique_caches;
	long status;
@@ -751,7 +762,7 @@ static void __init set_pci_cacheline_size(void)
			"(status=%ld)\n", __func__, status);
		return;
	}
	pci_cache_line_size = (1 << cci.pcci_line_size) / 4;
	pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
}

u64 ia64_dma_get_required_mask(struct device *dev)
@@ -782,7 +793,7 @@ EXPORT_SYMBOL_GPL(dma_get_required_mask);

static int __init pcibios_init(void)
{
	set_pci_cacheline_size();
	set_pci_dfl_cacheline_size();
	return 0;
}

+0 −2
Original line number Diff line number Diff line
@@ -16,8 +16,6 @@

#define PCI_IRQ_NONE		0xffffffff

#define PCI_CACHE_LINE_BYTES	64

static inline void pcibios_set_master(struct pci_dev *dev)
{
	/* No special bus mastering setup handling */
+7 −0
Original line number Diff line number Diff line
@@ -1081,3 +1081,10 @@ void pci_resource_to_user(const struct pci_dev *pdev, int bar,
	*start = rp->start - offset;
	*end = rp->end - offset;
}

static int __init pcibios_init(void)
{
	pci_dfl_cache_line_size = 64 >> 2;
	return 0;
}
subsys_initcall(pcibios_init);
+18 −2
Original line number Diff line number Diff line
@@ -118,11 +118,27 @@ extern int __init pcibios_init(void);

/* pci-mmconfig.c */

/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)

struct pci_mmcfg_region {
	struct list_head list;
	struct resource res;
	u64 address;
	char __iomem *virt;
	u16 segment;
	u8 start_bus;
	u8 end_bus;
	char name[PCI_MMCFG_RESOURCE_NAME_LEN];
};

extern int __init pci_mmcfg_arch_init(void);
extern void __init pci_mmcfg_arch_free(void);
extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);

extern struct list_head pci_mmcfg_list;

extern struct acpi_mcfg_allocation *pci_mmcfg_config;
extern int pci_mmcfg_config_num;
#define PCI_MMCFG_BUS_OFFSET(bus)      ((bus) << 20)

/*
 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
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