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Commit 1164ef78 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: expose ubwc version and ddr type through capability blob"

parents 00a590f4 ae545b1e
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+13 −0
Original line number Diff line number Diff line
@@ -4844,6 +4844,19 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
	if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3LITE)
		sde_kms_info_add_keystr(info, "qseed_type", "qseed3lite");

	sde_kms_info_add_keyint(info, "UBWC version", catalog->ubwc_version);
	sde_kms_info_add_keyint(info, "UBWC macrotile_mode",
				catalog->macrotile_mode);
	sde_kms_info_add_keyint(info, "UBWC highest banking bit",
				catalog->mdp[0].highest_bank_bit);
	sde_kms_info_add_keyint(info, "UBWC swizzle",
				catalog->mdp[0].ubwc_swizzle);

	if (of_fdt_get_ddrtype() == LP_DDR4_TYPE)
		sde_kms_info_add_keystr(info, "DDR version", "DDR4");
	else
		sde_kms_info_add_keystr(info, "DDR version", "DDR5");

	if (sde_is_custom_client()) {
		/* No support for SMART_DMA_V1 yet */
		if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@
#define _SDE_CRTC_H_

#include <linux/kthread.h>
#include <linux/of_fdt.h>
#include <drm/drm_crtc.h>
#include "msm_prop.h"
#include "sde_fence.h"
+2 −0
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@
#include "sde_hw_catalog.h"

#define REG_MASK(n)                     ((BIT(n)) - 1)
#define LP_DDR4_TYPE			0x4

struct sde_format_extended;

/*