Loading qcom/lito-camera.dtsi +21 −21 Original line number Diff line number Diff line Loading @@ -12,7 +12,7 @@ reg = <0x0ace0000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe0000>; interrupts = <0 477 0>; interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csiphy"; regulator-names = "gdscr", "refgen"; gdscr-supply = <&titan_top_gdsc>; Loading Loading @@ -42,7 +42,7 @@ reg = <0xace2000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe2000>; interrupts = <0 478 0>; interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csiphy"; regulator-names = "gdscr", "refgen"; gdscr-supply = <&titan_top_gdsc>; Loading Loading @@ -75,7 +75,7 @@ reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupts = <0 479 0>; interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csiphy"; regulator-names = "gdscr", "refgen"; gdscr-supply = <&titan_top_gdsc>; Loading Loading @@ -107,7 +107,7 @@ reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupts = <0 448 0>; interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csiphy"; regulator-names = "gdscr", "refgen"; gdscr-supply = <&titan_top_gdsc>; Loading Loading @@ -142,7 +142,7 @@ reg-names = "cci"; reg-cam-base = <0x4a000>; interrupt-names = "cci"; interrupts = <0 460 0>; interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; status = "ok"; gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; Loading Loading @@ -237,7 +237,7 @@ reg-names = "cci"; reg-cam-base = <0x4b000>; interrupt-names = "cci"; interrupts = <0 271 0>; interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; status = "ok"; gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; Loading Loading @@ -533,7 +533,7 @@ reg = <0xac48000 0x1000>; reg-names = "cpas-cdm"; reg-cam-base = <0x48000>; interrupts = <0 461 0>; interrupts = <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>; interrupt-names = "cpas-cdm"; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; Loading @@ -560,7 +560,7 @@ reg = <0xacb3000 0x1000>; reg-cam-base = <0xb3000>; interrupt-names = "csid"; interrupts = <0 464 0>; interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss", "ife0"; camss-supply = <&titan_top_gdsc>; ife0-supply = <&ife_0_gdsc>; Loading Loading @@ -598,7 +598,7 @@ reg = <0xacaf000 0x5200>; reg-cam-base = <0xaf000>; interrupt-names = "ife"; interrupts = <0 465 0>; interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss", "ife0"; camss-supply = <&titan_top_gdsc>; ife0-supply = <&ife_0_gdsc>; Loading Loading @@ -631,7 +631,7 @@ reg = <0xacba000 0x1000>; reg-cam-base = <0xba000>; interrupt-names = "csid"; interrupts = <0 466 0>; interrupts = <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss", "ife1"; camss-supply = <&titan_top_gdsc>; ife1-supply = <&ife_1_gdsc>; Loading Loading @@ -669,7 +669,7 @@ reg = <0xacb6000 0x5200>; reg-cam-base = <0xb6000>; interrupt-names = "ife"; interrupts = <0 467 0>; interrupts = <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss", "ife1"; camss-supply = <&titan_top_gdsc>; ife1-supply = <&ife_1_gdsc>; Loading Loading @@ -702,7 +702,7 @@ reg = <0xacc8000 0x1000>; reg-cam-base = <0xc8000>; interrupt-names = "csid-lite"; interrupts = <0 468 0>; interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; clock-names = Loading @@ -724,7 +724,7 @@ <384000000 0 0 0 400000000 0>, <400000000 0 0 0 480000000 0>, <400000000 0 0 0 600000000 0>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; Loading @@ -737,7 +737,7 @@ reg = <0xacc4000 0x4000>; reg-cam-base = <0xc4000>; interrupt-names = "ife-lite"; interrupts = <0 469 0>; interrupts = <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; clock-names = Loading @@ -751,7 +751,7 @@ <400000000 0>, <480000000 0>, <600000000 0>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; status = "ok"; Loading @@ -778,7 +778,7 @@ <0xac18000 0x3000>; reg-names = "a5_qgic", "a5_sierra", "a5_csr"; reg-cam-base = <0x00000 0x10000 0x18000>; interrupts = <0 463 0>; interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>; interrupt-names = "a5"; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; Loading Loading @@ -920,7 +920,7 @@ reg = <0xac4e000 0x4000>; reg-cam-base = <0x4e000>; interrupt-names = "jpeg"; interrupts = <0 474 0>; interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; clock-names = Loading @@ -943,7 +943,7 @@ reg = <0xac52000 0x4000>; reg-cam-base = <0x52000>; interrupt-names = "jpegdma"; interrupts = <0 475 0>; interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; clock-names = Loading Loading @@ -974,7 +974,7 @@ <0xac5b000 0x400>; reg-cam-base = <0x5a000 0x5b000>; interrupt-names = "fd"; interrupts = <0 462 0>; interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; clock-names = Loading Loading @@ -1009,7 +1009,7 @@ reg = <0xac6b000 0xa00>; reg-cam-base = <0x6b000>; interrupt-names = "lrme"; interrupts = <0 476 0>; interrupts = <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; clock-names = "lrme_clk_src", Loading Loading @@ -1038,7 +1038,7 @@ <0xac42000 0x6000>; reg-cam-base = <0x40000 0x42000>; interrupt-names = "cpas_camnoc"; interrupts = <0 459 0>; interrupts = <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>; camnoc-axi-min-ib-bw = <3000000000>; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; Loading Loading
qcom/lito-camera.dtsi +21 −21 Original line number Diff line number Diff line Loading @@ -12,7 +12,7 @@ reg = <0x0ace0000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe0000>; interrupts = <0 477 0>; interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csiphy"; regulator-names = "gdscr", "refgen"; gdscr-supply = <&titan_top_gdsc>; Loading Loading @@ -42,7 +42,7 @@ reg = <0xace2000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe2000>; interrupts = <0 478 0>; interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csiphy"; regulator-names = "gdscr", "refgen"; gdscr-supply = <&titan_top_gdsc>; Loading Loading @@ -75,7 +75,7 @@ reg = <0xace4000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe4000>; interrupts = <0 479 0>; interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csiphy"; regulator-names = "gdscr", "refgen"; gdscr-supply = <&titan_top_gdsc>; Loading Loading @@ -107,7 +107,7 @@ reg = <0xace6000 0x2000>; reg-names = "csiphy"; reg-cam-base = <0xe6000>; interrupts = <0 448 0>; interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>; interrupt-names = "csiphy"; regulator-names = "gdscr", "refgen"; gdscr-supply = <&titan_top_gdsc>; Loading Loading @@ -142,7 +142,7 @@ reg-names = "cci"; reg-cam-base = <0x4a000>; interrupt-names = "cci"; interrupts = <0 460 0>; interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; status = "ok"; gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; Loading Loading @@ -237,7 +237,7 @@ reg-names = "cci"; reg-cam-base = <0x4b000>; interrupt-names = "cci"; interrupts = <0 271 0>; interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; status = "ok"; gdscr-supply = <&titan_top_gdsc>; regulator-names = "gdscr"; Loading Loading @@ -533,7 +533,7 @@ reg = <0xac48000 0x1000>; reg-names = "cpas-cdm"; reg-cam-base = <0x48000>; interrupts = <0 461 0>; interrupts = <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>; interrupt-names = "cpas-cdm"; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; Loading @@ -560,7 +560,7 @@ reg = <0xacb3000 0x1000>; reg-cam-base = <0xb3000>; interrupt-names = "csid"; interrupts = <0 464 0>; interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss", "ife0"; camss-supply = <&titan_top_gdsc>; ife0-supply = <&ife_0_gdsc>; Loading Loading @@ -598,7 +598,7 @@ reg = <0xacaf000 0x5200>; reg-cam-base = <0xaf000>; interrupt-names = "ife"; interrupts = <0 465 0>; interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss", "ife0"; camss-supply = <&titan_top_gdsc>; ife0-supply = <&ife_0_gdsc>; Loading Loading @@ -631,7 +631,7 @@ reg = <0xacba000 0x1000>; reg-cam-base = <0xba000>; interrupt-names = "csid"; interrupts = <0 466 0>; interrupts = <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss", "ife1"; camss-supply = <&titan_top_gdsc>; ife1-supply = <&ife_1_gdsc>; Loading Loading @@ -669,7 +669,7 @@ reg = <0xacb6000 0x5200>; reg-cam-base = <0xb6000>; interrupt-names = "ife"; interrupts = <0 467 0>; interrupts = <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss", "ife1"; camss-supply = <&titan_top_gdsc>; ife1-supply = <&ife_1_gdsc>; Loading Loading @@ -702,7 +702,7 @@ reg = <0xacc8000 0x1000>; reg-cam-base = <0xc8000>; interrupt-names = "csid-lite"; interrupts = <0 468 0>; interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; clock-names = Loading @@ -724,7 +724,7 @@ <384000000 0 0 0 400000000 0>, <400000000 0 0 0 480000000 0>, <400000000 0 0 0 600000000 0>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_csid_clk_src"; clock-control-debugfs = "true"; status = "ok"; Loading @@ -737,7 +737,7 @@ reg = <0xacc4000 0x4000>; reg-cam-base = <0xc4000>; interrupt-names = "ife-lite"; interrupts = <0 469 0>; interrupts = <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; clock-names = Loading @@ -751,7 +751,7 @@ <400000000 0>, <480000000 0>, <600000000 0>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal"; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; src-clock-name = "ife_clk_src"; clock-control-debugfs = "true"; status = "ok"; Loading @@ -778,7 +778,7 @@ <0xac18000 0x3000>; reg-names = "a5_qgic", "a5_sierra", "a5_csr"; reg-cam-base = <0x00000 0x10000 0x18000>; interrupts = <0 463 0>; interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>; interrupt-names = "a5"; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; Loading Loading @@ -920,7 +920,7 @@ reg = <0xac4e000 0x4000>; reg-cam-base = <0x4e000>; interrupt-names = "jpeg"; interrupts = <0 474 0>; interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; clock-names = Loading @@ -943,7 +943,7 @@ reg = <0xac52000 0x4000>; reg-cam-base = <0x52000>; interrupt-names = "jpegdma"; interrupts = <0 475 0>; interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; clock-names = Loading Loading @@ -974,7 +974,7 @@ <0xac5b000 0x400>; reg-cam-base = <0x5a000 0x5b000>; interrupt-names = "fd"; interrupts = <0 462 0>; interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; clock-names = Loading Loading @@ -1009,7 +1009,7 @@ reg = <0xac6b000 0xa00>; reg-cam-base = <0x6b000>; interrupt-names = "lrme"; interrupts = <0 476 0>; interrupts = <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>; regulator-names = "camss"; camss-supply = <&titan_top_gdsc>; clock-names = "lrme_clk_src", Loading Loading @@ -1038,7 +1038,7 @@ <0xac42000 0x6000>; reg-cam-base = <0x40000 0x42000>; interrupt-names = "cpas_camnoc"; interrupts = <0 459 0>; interrupts = <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>; camnoc-axi-min-ib-bw = <3000000000>; regulator-names = "camss-vdd"; camss-vdd-supply = <&titan_top_gdsc>; Loading