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Commit 1159e094 authored by Harry Pan's avatar Harry Pan Committed by Ingo Molnar
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perf/x86/intel: Enable C-state residency events for Cannon Lake 



Cannon Lake supports C1/C3/C6/C7, PC2/PC3/PC6/PC7/PC8/PC9/PC10
state residency counters, this patch enables those counters.

( The MSR information is based on Intel Software Developers' Manual,
  Vol. 4, Order No. 335592. )

Tested-by: default avatarPuthikorn Voravootivat <puthik@chromium.org>
Signed-off-by: default avatarHarry Pan <harry.pan@intel.com>
Reviewed-by: default avatarBenson Leung <bleung@chromium.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan.liang@intel.com
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: gs0622@gmail.com
Link: http://lkml.kernel.org/r/20180309121549.630-3-harry.pan@intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent 490d03e8

arch/x86/events/intel/cstate.c

+31 −13
Original line number Diff line number Diff line
@@ -40,50 +40,51 @@ 
 * Model specific counters:

 *	MSR_CORE_C1_RES: CORE C1 Residency Counter

 *			 perf code: 0x00

 *			 Available model: SLM,AMT,GLM

 *			 Available model: SLM,AMT,GLM,CNL

 *			 Scope: Core (each processor core has a MSR)

 *	MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter

 *			       perf code: 0x01

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,

						CNL

 *			       Scope: Core

 *	MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW

 *						SKL,KNL,GLM

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW,

 *						SKL,KNL,GLM,CNL

 *			       Scope: Core

 *	MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter

 *			       perf code: 0x03

 *			       Available model: SNB,IVB,HSW,BDW,SKL

 *			       Available model: SNB,IVB,HSW,BDW,SKL,CNL

 *			       Scope: Core

 *	MSR_PKG_C2_RESIDENCY:  Package C2 Residency Counter.

 *			       perf code: 0x00

 *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM

 *			       Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C3_RESIDENCY:  Package C3 Residency Counter.

 *			       perf code: 0x01

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL

 *						GLM

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL,

 *						GLM,CNL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C6_RESIDENCY:  Package C6 Residency Counter.

 *			       perf code: 0x02

 *			       Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW

 *						SKL,KNL,GLM

 *						SKL,KNL,GLM,CNL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C7_RESIDENCY:  Package C7 Residency Counter.

 *			       perf code: 0x03

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL

 *			       Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,CNL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C8_RESIDENCY:  Package C8 Residency Counter.

 *			       perf code: 0x04

 *			       Available model: HSW ULT only

 *			       Available model: HSW ULT,CNL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C9_RESIDENCY:  Package C9 Residency Counter.

 *			       perf code: 0x05

 *			       Available model: HSW ULT only

 *			       Available model: HSW ULT,CNL

 *			       Scope: Package (physical package)

 *	MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter.

 *			       perf code: 0x06

 *			       Available model: HSW ULT, GLM

 *			       Available model: HSW ULT,GLM,CNL

 *			       Scope: Package (physical package)

 *

 */
@@ -486,6 +487,21 @@ static const struct cstate_model hswult_cstates __initconst = { 
				  BIT(PERF_CSTATE_PKG_C10_RES),

};



static const struct cstate_model cnl_cstates __initconst = {

	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |

				  BIT(PERF_CSTATE_CORE_C3_RES) |

				  BIT(PERF_CSTATE_CORE_C6_RES) |

				  BIT(PERF_CSTATE_CORE_C7_RES),



	.pkg_events		= BIT(PERF_CSTATE_PKG_C2_RES) |

				  BIT(PERF_CSTATE_PKG_C3_RES) |

				  BIT(PERF_CSTATE_PKG_C6_RES) |

				  BIT(PERF_CSTATE_PKG_C7_RES) |

				  BIT(PERF_CSTATE_PKG_C8_RES) |

				  BIT(PERF_CSTATE_PKG_C9_RES) |

				  BIT(PERF_CSTATE_PKG_C10_RES),

};



static const struct cstate_model slm_cstates __initconst = {

	.core_events		= BIT(PERF_CSTATE_CORE_C1_RES) |

				  BIT(PERF_CSTATE_CORE_C6_RES),
@@ -557,6 +573,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE,  snb_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),



	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),

	X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),