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Commit 10d77ec2 authored by Haojian Zhuang's avatar Haojian Zhuang Committed by Haojian Zhuang
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ARM: dts: append DTS file of pxa168 



DTS files of both PXA168 and aspenite are appended.

Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@marvell.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 5d489766

arch/arm/boot/dts/pxa168-aspenite.dts

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/*

 *  Copyright (C) 2012 Marvell Technology Group Ltd.

 *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>

 *

 *  This program is free software; you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License version 2 as

 *  publishhed by the Free Software Foundation.

 */



/dts-v1/;

/include/ "pxa168.dtsi"



/ {

	model = "Marvell PXA168 Aspenite Development Board";

	compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";



	chosen {

		bootargs = "console=ttyS0,115200 root=/dev/nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on";

	};



	memory {

		reg = <0x00000000 0x04000000>;

	};



	soc {

		apb@d4000000 {

			uart1: uart@d4017000 {

				status = "okay";

			};

			twsi1: i2c@d4011000 {

				status = "okay";

			};

			rtc: rtc@d4010000 {

				status = "okay";

			};

		};

	};

};

arch/arm/boot/dts/pxa168.dtsi

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/*

 *  Copyright (C) 2012 Marvell Technology Group Ltd.

 *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>

 *

 *  This program is free software; you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License version 2 as

 *  publishhed by the Free Software Foundation.

 */



/include/ "skeleton.dtsi"



/ {

	aliases {

		serial0 = &uart1;

		serial1 = &uart2;

		serial2 = &uart3;

		i2c0 = &twsi1;

		i2c1 = &twsi2;

	};



	intc: intc-interrupt-controller@d4282000 {

		compatible = "mrvl,mmp-intc", "mrvl,intc";

		interrupt-controller;

		#interrupt-cells = <1>;

		reg = <0xd4282000 0x1000>;

	};



	soc {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "simple-bus";

		interrupt-parent = <&intc>;

		ranges;



		apb@d4000000 {	/* APB */

			compatible = "mrvl,apb-bus", "simple-bus";

			#address-cells = <1>;

			#size-cells = <1>;

			reg = <0xd4000000 0x00200000>;

			ranges;



			uart1: uart@d4017000 {

				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";

				reg = <0xd4017000 0x1000>;

				interrupts = <27>;

				status = "disabled";

			};



			uart2: uart@d4018000 {

				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";

				reg = <0xd4018000 0x1000>;

				interrupts = <28>;

				status = "disabled";

			};



			uart3: uart@d4026000 {

				compatible = "mrvl,mmp-uart", "mrvl,pxa-uart";

				reg = <0xd4026000 0x1000>;

				interrupts = <29>;

				status = "disabled";

			};



			gpio: gpio@d4019000 {

				compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio";

				reg = <0xd4019000 0x1000>;

				interrupts = <49>;

				interrupt-names = "gpio_mux";

				gpio-controller;

				#gpio-cells = <1>;

				interrupt-controller;

				#interrupt-cells = <1>;

			};



			twsi1: i2c@d4011000 {

				compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";

				reg = <0xd4011000 0x1000>;

				interrupts = <7>;

				mrvl,i2c-fast-mode;

				status = "disabled";

			};



			twsi2: i2c@d4025000 {

				compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c";

				reg = <0xd4025000 0x1000>;

				interrupts = <58>;

				status = "disabled";

			};



			rtc: rtc@d4010000 {

				compatible = "mrvl,mmp-rtc";

				reg = <0xd4010000 0x1000>;

				interrupts = <5 6>;

				interrupt-names = "rtc 1Hz", "rtc alarm";

				status = "disabled";

			};

		};

	};

};