Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 1068ec79 authored by Antoine Tenart's avatar Antoine Tenart Committed by David S. Miller
Browse files

net: mvpp2: fix the synchronization module bypass macro name 



The macro defining the bit to toggle to bypass or not the
synchronization module is wrongly named. Writing 1 will disable bypass.
This patch s/MVPP22_CTRL4_SYNC_BYPASS/MVPP22_CTRL4_SYNC_BYPASS_DIS/.

Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Tested-by: default avatarMarcin Wojtas <mw@semihalf.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 81b6630f

drivers/net/ethernet/marvell/mvpp2.c

+2 −2
Original line number Diff line number Diff line
@@ -346,7 +346,7 @@ 
#define MVPP22_GMAC_CTRL_4_REG			0x90

#define     MVPP22_CTRL4_EXT_PIN_GMII_SEL	BIT(0)

#define     MVPP22_CTRL4_DP_CLK_SEL		BIT(5)

#define     MVPP22_CTRL4_SYNC_BYPASS		BIT(6)

#define     MVPP22_CTRL4_SYNC_BYPASS_DIS	BIT(6)

#define     MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE	BIT(7)



/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
@@ -4269,7 +4269,7 @@ static void mvpp22_port_mii_set(struct mvpp2_port *port) 
	else

		val &= ~MVPP22_CTRL4_EXT_PIN_GMII_SEL;

	val &= ~MVPP22_CTRL4_DP_CLK_SEL;

	val |= MVPP22_CTRL4_SYNC_BYPASS;

	val |= MVPP22_CTRL4_SYNC_BYPASS_DIS;

	val |= MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;

	writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);

}