Loading fw/dbglog.h +3 −0 Original line number Diff line number Diff line /* * Copyright (c) 2012-2016 The Linux Foundation. All rights reserved. * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * Loading Loading @@ -32,6 +33,8 @@ #include "athstartpack.h" #endif #include <a_types.h> /* A_UINT32 */ #include <a_osapi.h> /* PREPACK */ #include <wlan_module_ids.h> #ifdef __cplusplus Loading fw/htt.h +3 −1 Original line number Diff line number Diff line Loading @@ -262,9 +262,10 @@ * 3.132 Add flow_classification_3_tuple_field_enable in H2T 3_TUPLE_HASH_CFG. * 3.133 Add packet_type_enable_data_flags fields in rx_ring_selection_cfg. * 3.134 Add qdata_refill flag in rx_peer_metadata_v1a. * 3.135 Add HTT_HOST4_TO_FW_RXBUF_RING def. */ #define HTT_CURRENT_VERSION_MAJOR 3 #define HTT_CURRENT_VERSION_MINOR 134 #define HTT_CURRENT_VERSION_MINOR 135 #define HTT_NUM_TX_FRAG_DESC 1024 Loading Loading @@ -5454,6 +5455,7 @@ enum htt_srng_ring_id { HTT_RX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */ HTT_LPASS_TO_FW_RXBUF_RING, /* new LPASS to FW refill ring to recycle rx buffers */ HTT_HOST3_TO_FW_RXBUF_RING, /* used by host for EasyMesh feature */ HTT_HOST4_TO_FW_RXBUF_RING, /* fourth ring used by host to provide buffers for MGMT packets */ /* Add Other SRING which can't be directly configured by host software above this line */ }; fw/htt_stats.h +232 −0 Original line number Diff line number Diff line Loading @@ -9142,6 +9142,200 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv; #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_M 0x00000001 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S 0 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_M) >> \ HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S) #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)); \ } while (0) #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M 0x00000006 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S 1 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M) >> \ HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S) #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_SOURCE, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_SOURCE_S)); \ } while (0) #define HTT_STATS_PHY_RESET_XTALCAL_M 0x00000008 #define HTT_STATS_PHY_RESET_XTALCAL_S 3 #define HTT_STATS_PHY_RESET_XTALCAL_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_XTALCAL_M) >> \ HTT_STATS_PHY_RESET_XTALCAL_S) #define HTT_STATS_PHY_RESET_XTALCAL_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTALCAL, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_XTALCAL_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000010 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 4 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL2GOPC_S) #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GOPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GOPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000020 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 5 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GFPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL2GFPC_S) #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GFPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GFPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000040 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 6 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL5GOPC_S) #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GOPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GOPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000080 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 7 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GFPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL5GFPC_S) #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GFPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GFPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000100 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 8 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL6GOPC_S) #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GOPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GOPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_M 0x00000200 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_S 9 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GFPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL6GFPC_S) #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GFPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GFPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_RXGAINCAL2G_M 0x00000400 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_S 10 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL2G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL2G_S) #define HTT_STATS_PHY_RESET_RXGAINCAL2G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL2G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL2G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_RXGAINCAL5G_M 0x00000800 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_S 11 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL5G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL5G_S) #define HTT_STATS_PHY_RESET_RXGAINCAL5G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL5G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL5G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_RXGAINCAL6G_M 0x00001000 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_S 12 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL6G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL6G_S) #define HTT_STATS_PHY_RESET_RXGAINCAL6G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL6G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL6G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_AOACAL2G_M 0x00002000 #define HTT_STATS_PHY_RESET_AOACAL2G_S 13 #define HTT_STATS_PHY_RESET_AOACAL2G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL2G_M) >> \ HTT_STATS_PHY_RESET_AOACAL2G_S) #define HTT_STATS_PHY_RESET_AOACAL2G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL2G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL2G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_AOACAL5G_M 0x00004000 #define HTT_STATS_PHY_RESET_AOACAL5G_S 14 #define HTT_STATS_PHY_RESET_AOACAL5G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL5G_M) >> \ HTT_STATS_PHY_RESET_AOACAL5G_S) #define HTT_STATS_PHY_RESET_AOACAL5G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL5G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL5G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_AOACAL6G_M 0x00008000 #define HTT_STATS_PHY_RESET_AOACAL6G_S 15 #define HTT_STATS_PHY_RESET_AOACAL6G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL6G_M) >> \ HTT_STATS_PHY_RESET_AOACAL6G_S) #define HTT_STATS_PHY_RESET_AOACAL6G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL6G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL6G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M 0x00010000 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S 16 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M) >> \ HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S) #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTAL_FROM_OTP, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_XTAL_FROM_OTP_S)); \ } while (0) #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_M 0x000000FF #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_S 0 #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_GLUT_LINEARITY_M) >> \ HTT_STATS_PHY_RESET_GLUT_LINEARITY_S) #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_GLUT_LINEARITY, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_GLUT_LINEARITY_S)); \ } while (0) #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_M 0x0000FF00 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_S 8 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_PLUT_LINEARITY_M) >> \ HTT_STATS_PHY_RESET_PLUT_LINEARITY_S) #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_PLUT_LINEARITY, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_PLUT_LINEARITY_S)); \ } while (0) #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_M 0x00FF0000 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_S 16 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_WLANDRIVERMODE_M) >> \ HTT_STATS_PHY_RESET_WLANDRIVERMODE_S) #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_WLANDRIVERMODE, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_WLANDRIVERMODE_S)); \ } while (0) typedef struct { htt_tlv_hdr_t tlv_hdr; /** current pdev_id */ Loading Loading @@ -9260,6 +9454,44 @@ typedef struct { * when explicitly requested by the host. */ A_UINT32 nfcal_iteration_counts[3]; /** Below union indicates the merge status for different cal */ union { A_UINT32 calmerge_stats; struct { A_UINT32 CalData_Compressed:1, CalDataSource:2, xtalcal:1, tpccal2GFPC:1, tpccal2GOPC:1, tpccal5GFPC:1, tpccal5GOPC:1, tpccal6GFPC:1, tpccal6GOPC:1, rxgaincal2G:1, rxgaincal5G:1, rxgaincal6G:1, aoacal2G:1, aoacal5G:1, aoacal6G:1, XTAL_from_OTP:1, rsvd1:15; }; }; /** Below union lets us know of any non-linearity in plut/glut * and the mode we are in */ union { A_UINT32 misc_stats; struct { A_UINT32 GLUT_linearity:8, PLUT_linearity:8, WlanDriverMode:8, rsvd2:8; }; }; /** BoardId fetched from OTP */ A_UINT32 BoardIDfromOTP; } htt_stats_phy_reset_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_phy_reset_stats_tlv htt_phy_reset_stats_tlv; Loading fw/wlan_module_ids.h +36 −0 Original line number Diff line number Diff line Loading @@ -156,6 +156,42 @@ typedef enum { WLAN_MODULE_AUX_MAC_MGR, /* 0x73 */ WLAN_MODULE_TCAM, /* 0x74 */ WLAN_MODULE_P2P_R2, /* 0x75 */ WLAN_MODULE_SYSSW, /* 0x76 */ /* HDL MODULE IDS */ WLAN_MODULE_PHYLIB_RXDCOCAL, /* 0x77 */ WLAN_MODULE_PHYLIB_COMBCAL, /* 0x78 */ WLAN_MODULE_PHYLIB_TPCCAL, /* 0x79 */ WLAN_MODULE_PHYLIB_BBFILTCAL, /* 0x7a */ WLAN_MODULE_PHYLIB_PKTDETCAL, /* 0x7b */ WLAN_MODULE_PHYLIB_PAPRDCAL, /* 0x7c */ WLAN_MODULE_PHYLIB_NFCAL, /* 0x7d */ WLAN_MODULE_PHYLIB_ADCCAL, /* 0x7e */ WLAN_MODULE_PHYLIB_DACCAL, /* 0x7f */ WLAN_MODULE_PHYLIB_PALCAL, /* 0x80 */ WLAN_MODULE_PHYLIB_RXGAINCAL, /* 0x81 */ WLAN_MODULE_PHYLIB_CALUTILS, /* 0x82 */ WLAN_MODULE_PHYLIB_PHYRESET, /* 0x83 */ WLAN_MODULE_PHYLIB_RFACONFIG, /* 0x84 */ WLAN_MODULE_PHYLIB_SETCHAINMASK, /* 0x85 */ WLAN_MODULE_PHYLIB_SETXBAR, /* 0x86 */ WLAN_MODULE_PHYLIB_M3, /* 0x87 */ WLAN_MODULE_PHYLIB_COMMON, /* 0x88 */ WLAN_MODULE_PHYLIB_SPURMITT, /* 0x89 */ WLAN_MODULE_PHYLIB_RTT, /* 0x8a */ WLAN_MODULE_PHYLIB_FTPG, /* 0x8b */ WLAN_MODULE_PHYLIB_RSTCAL, /* 0x8c */ WLAN_MODULE_PHYLIB_RXBBFCAL, /* 0x8d */ WLAN_MODULE_PHYLIB_TIADCCAL, /* 0x8e */ WLAN_MODULE_PHYLIB_IM2CAL, /* 0x8f */ WLAN_MODULE_PHYLIB_PACCAL, /* 0x90 */ WLAN_MODULE_PHYLIB_PDCCAL, /* 0x91 */ WLAN_MODULE_PHYLIB_SPURCAL, /* 0x92 */ WLAN_MODULE_PHYLIB_PHYDBG, /* 0x93 */ WLAN_MODULE_PHYLIB_RRI, /* 0x94 */ WLAN_MODULE_PHYLIB_SSCAN, /* 0x95 */ WLAN_MODULE_PHYLIB_RSVD, /* 0x96 */ WLAN_MODULE_ID_MAX, WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX, Loading fw/wmi_services.h +4 −0 Original line number Diff line number Diff line Loading @@ -670,6 +670,10 @@ typedef enum { WMI_SERVICE_USE_STA_VDEV_FOR_P2P_DEVICE = 416, /* FW supports use of sta vdev to be repurposed for p2p device */ WMI_SERVICE_AP_ASSISTED_DFS_CHAN_P2P_SESSION = 417, /* FW supports P2P session on DFS chan enabled by DFS master AP */ WMI_SERVICE_MLO_SAP_EMLSR_SUPPORT = 418, /* Indicates FW MLO SAP supports EMLSR Mode */ WMI_SERVICE_PKTLOG_ML_TSTMP_SUPPORT = 419, /* Indicates ML timestamp for pktlog */ WMI_SERVICE_MGMT_SRNG_SUPPORT = 420, /* FW supports MGMT frame forwarding via host provided SRNG instead of WMI */ WMI_SERVICE_WDS_NULL_FRAME_SUPPORT = 421, WMI_SERVICE_MLO_SAP_CONCURRENCY_SUPPORT = 422, /* Indicates FW supports MLO SAP+STA Concurrency */ WMI_MAX_EXT2_SERVICE Loading Loading
fw/dbglog.h +3 −0 Original line number Diff line number Diff line /* * Copyright (c) 2012-2016 The Linux Foundation. All rights reserved. * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * Loading Loading @@ -32,6 +33,8 @@ #include "athstartpack.h" #endif #include <a_types.h> /* A_UINT32 */ #include <a_osapi.h> /* PREPACK */ #include <wlan_module_ids.h> #ifdef __cplusplus Loading
fw/htt.h +3 −1 Original line number Diff line number Diff line Loading @@ -262,9 +262,10 @@ * 3.132 Add flow_classification_3_tuple_field_enable in H2T 3_TUPLE_HASH_CFG. * 3.133 Add packet_type_enable_data_flags fields in rx_ring_selection_cfg. * 3.134 Add qdata_refill flag in rx_peer_metadata_v1a. * 3.135 Add HTT_HOST4_TO_FW_RXBUF_RING def. */ #define HTT_CURRENT_VERSION_MAJOR 3 #define HTT_CURRENT_VERSION_MINOR 134 #define HTT_CURRENT_VERSION_MINOR 135 #define HTT_NUM_TX_FRAG_DESC 1024 Loading Loading @@ -5454,6 +5455,7 @@ enum htt_srng_ring_id { HTT_RX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */ HTT_LPASS_TO_FW_RXBUF_RING, /* new LPASS to FW refill ring to recycle rx buffers */ HTT_HOST3_TO_FW_RXBUF_RING, /* used by host for EasyMesh feature */ HTT_HOST4_TO_FW_RXBUF_RING, /* fourth ring used by host to provide buffers for MGMT packets */ /* Add Other SRING which can't be directly configured by host software above this line */ };
fw/htt_stats.h +232 −0 Original line number Diff line number Diff line Loading @@ -9142,6 +9142,200 @@ typedef struct { /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_phy_stats_tlv htt_phy_stats_tlv; #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_M 0x00000001 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S 0 #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_M) >> \ HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_S) #define HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_COMPRESSED, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_COMPRESSED_S)); \ } while (0) #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M 0x00000006 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S 1 #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_M) >> \ HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_S) #define HTT_STATS_PHY_RESET_CAL_DATA_SOURCE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_CAL_DATA_SOURCE, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_CAL_DATA_SOURCE_S)); \ } while (0) #define HTT_STATS_PHY_RESET_XTALCAL_M 0x00000008 #define HTT_STATS_PHY_RESET_XTALCAL_S 3 #define HTT_STATS_PHY_RESET_XTALCAL_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_XTALCAL_M) >> \ HTT_STATS_PHY_RESET_XTALCAL_S) #define HTT_STATS_PHY_RESET_XTALCAL_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTALCAL, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_XTALCAL_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_M 0x00000010 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_S 4 #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL2GOPC_S) #define HTT_STATS_PHY_RESET_TPCCAL2GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GOPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GOPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_M 0x00000020 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_S 5 #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL2GFPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL2GFPC_S) #define HTT_STATS_PHY_RESET_TPCCAL2GFPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL2GFPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL2GFPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_M 0x00000040 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_S 6 #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL5GOPC_S) #define HTT_STATS_PHY_RESET_TPCCAL5GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GOPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GOPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_M 0x00000080 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_S 7 #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL5GFPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL5GFPC_S) #define HTT_STATS_PHY_RESET_TPCCAL5GFPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL5GFPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL5GFPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_M 0x00000100 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_S 8 #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GOPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL6GOPC_S) #define HTT_STATS_PHY_RESET_TPCCAL6GOPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GOPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GOPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_M 0x00000200 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_S 9 #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_TPCCAL6GFPC_M) >> \ HTT_STATS_PHY_RESET_TPCCAL6GFPC_S) #define HTT_STATS_PHY_RESET_TPCCAL6GFPC_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_TPCCAL6GFPC, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_TPCCAL6GFPC_S)); \ } while (0) #define HTT_STATS_PHY_RESET_RXGAINCAL2G_M 0x00000400 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_S 10 #define HTT_STATS_PHY_RESET_RXGAINCAL2G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL2G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL2G_S) #define HTT_STATS_PHY_RESET_RXGAINCAL2G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL2G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL2G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_RXGAINCAL5G_M 0x00000800 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_S 11 #define HTT_STATS_PHY_RESET_RXGAINCAL5G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL5G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL5G_S) #define HTT_STATS_PHY_RESET_RXGAINCAL5G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL5G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL5G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_RXGAINCAL6G_M 0x00001000 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_S 12 #define HTT_STATS_PHY_RESET_RXGAINCAL6G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_RXGAINCAL6G_M) >> \ HTT_STATS_PHY_RESET_RXGAINCAL6G_S) #define HTT_STATS_PHY_RESET_RXGAINCAL6G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_RXGAINCAL6G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_RXGAINCAL6G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_AOACAL2G_M 0x00002000 #define HTT_STATS_PHY_RESET_AOACAL2G_S 13 #define HTT_STATS_PHY_RESET_AOACAL2G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL2G_M) >> \ HTT_STATS_PHY_RESET_AOACAL2G_S) #define HTT_STATS_PHY_RESET_AOACAL2G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL2G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL2G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_AOACAL5G_M 0x00004000 #define HTT_STATS_PHY_RESET_AOACAL5G_S 14 #define HTT_STATS_PHY_RESET_AOACAL5G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL5G_M) >> \ HTT_STATS_PHY_RESET_AOACAL5G_S) #define HTT_STATS_PHY_RESET_AOACAL5G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL5G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL5G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_AOACAL6G_M 0x00008000 #define HTT_STATS_PHY_RESET_AOACAL6G_S 15 #define HTT_STATS_PHY_RESET_AOACAL6G_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_AOACAL6G_M) >> \ HTT_STATS_PHY_RESET_AOACAL6G_S) #define HTT_STATS_PHY_RESET_AOACAL6G_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_AOACAL6G, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_AOACAL6G_S)); \ } while (0) #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M 0x00010000 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S 16 #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_XTAL_FROM_OTP_M) >> \ HTT_STATS_PHY_RESET_XTAL_FROM_OTP_S) #define HTT_STATS_PHY_RESET_XTAL_FROM_OTP_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_XTAL_FROM_OTP, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_XTAL_FROM_OTP_S)); \ } while (0) #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_M 0x000000FF #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_S 0 #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_GLUT_LINEARITY_M) >> \ HTT_STATS_PHY_RESET_GLUT_LINEARITY_S) #define HTT_STATS_PHY_RESET_GLUT_LINEARITY_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_GLUT_LINEARITY, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_GLUT_LINEARITY_S)); \ } while (0) #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_M 0x0000FF00 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_S 8 #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_PLUT_LINEARITY_M) >> \ HTT_STATS_PHY_RESET_PLUT_LINEARITY_S) #define HTT_STATS_PHY_RESET_PLUT_LINEARITY_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_PLUT_LINEARITY, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_PLUT_LINEARITY_S)); \ } while (0) #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_M 0x00FF0000 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_S 16 #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_GET(_var) \ (((_var) & HTT_STATS_PHY_RESET_WLANDRIVERMODE_M) >> \ HTT_STATS_PHY_RESET_WLANDRIVERMODE_S) #define HTT_STATS_PHY_RESET_WLANDRIVERMODE_SET(_var, _val) \ do { \ HTT_CHECK_SET_VAL(HTT_STATS_PHY_RESET_WLANDRIVERMODE, _val); \ ((_var) |= ((_val) << STATS_PHY_RESET_WLANDRIVERMODE_S)); \ } while (0) typedef struct { htt_tlv_hdr_t tlv_hdr; /** current pdev_id */ Loading Loading @@ -9260,6 +9454,44 @@ typedef struct { * when explicitly requested by the host. */ A_UINT32 nfcal_iteration_counts[3]; /** Below union indicates the merge status for different cal */ union { A_UINT32 calmerge_stats; struct { A_UINT32 CalData_Compressed:1, CalDataSource:2, xtalcal:1, tpccal2GFPC:1, tpccal2GOPC:1, tpccal5GFPC:1, tpccal5GOPC:1, tpccal6GFPC:1, tpccal6GOPC:1, rxgaincal2G:1, rxgaincal5G:1, rxgaincal6G:1, aoacal2G:1, aoacal5G:1, aoacal6G:1, XTAL_from_OTP:1, rsvd1:15; }; }; /** Below union lets us know of any non-linearity in plut/glut * and the mode we are in */ union { A_UINT32 misc_stats; struct { A_UINT32 GLUT_linearity:8, PLUT_linearity:8, WlanDriverMode:8, rsvd2:8; }; }; /** BoardId fetched from OTP */ A_UINT32 BoardIDfromOTP; } htt_stats_phy_reset_stats_tlv; /* preserve old name alias for new name consistent with the tag name */ typedef htt_stats_phy_reset_stats_tlv htt_phy_reset_stats_tlv; Loading
fw/wlan_module_ids.h +36 −0 Original line number Diff line number Diff line Loading @@ -156,6 +156,42 @@ typedef enum { WLAN_MODULE_AUX_MAC_MGR, /* 0x73 */ WLAN_MODULE_TCAM, /* 0x74 */ WLAN_MODULE_P2P_R2, /* 0x75 */ WLAN_MODULE_SYSSW, /* 0x76 */ /* HDL MODULE IDS */ WLAN_MODULE_PHYLIB_RXDCOCAL, /* 0x77 */ WLAN_MODULE_PHYLIB_COMBCAL, /* 0x78 */ WLAN_MODULE_PHYLIB_TPCCAL, /* 0x79 */ WLAN_MODULE_PHYLIB_BBFILTCAL, /* 0x7a */ WLAN_MODULE_PHYLIB_PKTDETCAL, /* 0x7b */ WLAN_MODULE_PHYLIB_PAPRDCAL, /* 0x7c */ WLAN_MODULE_PHYLIB_NFCAL, /* 0x7d */ WLAN_MODULE_PHYLIB_ADCCAL, /* 0x7e */ WLAN_MODULE_PHYLIB_DACCAL, /* 0x7f */ WLAN_MODULE_PHYLIB_PALCAL, /* 0x80 */ WLAN_MODULE_PHYLIB_RXGAINCAL, /* 0x81 */ WLAN_MODULE_PHYLIB_CALUTILS, /* 0x82 */ WLAN_MODULE_PHYLIB_PHYRESET, /* 0x83 */ WLAN_MODULE_PHYLIB_RFACONFIG, /* 0x84 */ WLAN_MODULE_PHYLIB_SETCHAINMASK, /* 0x85 */ WLAN_MODULE_PHYLIB_SETXBAR, /* 0x86 */ WLAN_MODULE_PHYLIB_M3, /* 0x87 */ WLAN_MODULE_PHYLIB_COMMON, /* 0x88 */ WLAN_MODULE_PHYLIB_SPURMITT, /* 0x89 */ WLAN_MODULE_PHYLIB_RTT, /* 0x8a */ WLAN_MODULE_PHYLIB_FTPG, /* 0x8b */ WLAN_MODULE_PHYLIB_RSTCAL, /* 0x8c */ WLAN_MODULE_PHYLIB_RXBBFCAL, /* 0x8d */ WLAN_MODULE_PHYLIB_TIADCCAL, /* 0x8e */ WLAN_MODULE_PHYLIB_IM2CAL, /* 0x8f */ WLAN_MODULE_PHYLIB_PACCAL, /* 0x90 */ WLAN_MODULE_PHYLIB_PDCCAL, /* 0x91 */ WLAN_MODULE_PHYLIB_SPURCAL, /* 0x92 */ WLAN_MODULE_PHYLIB_PHYDBG, /* 0x93 */ WLAN_MODULE_PHYLIB_RRI, /* 0x94 */ WLAN_MODULE_PHYLIB_SSCAN, /* 0x95 */ WLAN_MODULE_PHYLIB_RSVD, /* 0x96 */ WLAN_MODULE_ID_MAX, WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX, Loading
fw/wmi_services.h +4 −0 Original line number Diff line number Diff line Loading @@ -670,6 +670,10 @@ typedef enum { WMI_SERVICE_USE_STA_VDEV_FOR_P2P_DEVICE = 416, /* FW supports use of sta vdev to be repurposed for p2p device */ WMI_SERVICE_AP_ASSISTED_DFS_CHAN_P2P_SESSION = 417, /* FW supports P2P session on DFS chan enabled by DFS master AP */ WMI_SERVICE_MLO_SAP_EMLSR_SUPPORT = 418, /* Indicates FW MLO SAP supports EMLSR Mode */ WMI_SERVICE_PKTLOG_ML_TSTMP_SUPPORT = 419, /* Indicates ML timestamp for pktlog */ WMI_SERVICE_MGMT_SRNG_SUPPORT = 420, /* FW supports MGMT frame forwarding via host provided SRNG instead of WMI */ WMI_SERVICE_WDS_NULL_FRAME_SUPPORT = 421, WMI_SERVICE_MLO_SAP_CONCURRENCY_SUPPORT = 422, /* Indicates FW supports MLO SAP+STA Concurrency */ WMI_MAX_EXT2_SERVICE Loading