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Commit 1052cff3 authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Kukjin Kim
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ARM: S5P: fix offset calculation on gpio-interrupt 



Offsets of the irq controller registers were calculated
correctly only for first GPIO bank. This patch fixes
calculation of the register offsets for all GPIO banks.

Reported-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: default avatarKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 899e3ee4

arch/arm/plat-s5p/irq-gpioint.c

+3 −3
Original line number Diff line number Diff line
@@ -163,9 +163,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) 
	ct->chip.irq_mask = irq_gc_mask_set_bit;

	ct->chip.irq_unmask = irq_gc_mask_clr_bit;

	ct->chip.irq_set_type = s5p_gpioint_set_type,

	ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);

	ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);

	ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);

	ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);

	ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);

	ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);

	irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),

			       IRQ_GC_INIT_MASK_CACHE,

			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);