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Commit 1038df1f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "asoc: bolero: Update rx dc droop register setting"

parents a715bed4 80581c4b
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+13 −11
Original line number Diff line number Diff line
@@ -1687,13 +1687,6 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
	dev_dbg(component->dev, "%s: event %d compander %d, enabled %d\n",
		__func__, event, comp + 1, rx_priv->comp_enabled[comp]);

	if (!rx_priv->comp_enabled[comp])
		return 0;

	comp_ctl0_reg = BOLERO_CDC_RX_COMPANDER0_CTL0 +
					(comp * RX_MACRO_COMP_OFFSET);
	rx_path_cfg0_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG0 +
					(comp * RX_MACRO_RX_PATH_OFFSET);
	rx_path_cfg3_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG3 +
					(comp * RX_MACRO_RX_PATH_OFFSET);
	rx0_path_ctl_reg = BOLERO_CDC_RX_RX0_RX_PATH_CTL +
@@ -1709,6 +1702,19 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
	else
		val = 0x00;

	if (SND_SOC_DAPM_EVENT_ON(event))
		snd_soc_component_update_bits(component, rx_path_cfg3_reg,
					0x03, val);
	if (SND_SOC_DAPM_EVENT_OFF(event))
		snd_soc_component_update_bits(component, rx_path_cfg3_reg,
					0x03, 0x03);
	if (!rx_priv->comp_enabled[comp])
		return 0;

	comp_ctl0_reg = BOLERO_CDC_RX_COMPANDER0_CTL0 +
					(comp * RX_MACRO_COMP_OFFSET);
	rx_path_cfg0_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG0 +
					(comp * RX_MACRO_RX_PATH_OFFSET);
	if (SND_SOC_DAPM_EVENT_ON(event)) {
		/* Enable Compander Clock */
		snd_soc_component_update_bits(component, comp_ctl0_reg,
@@ -1719,8 +1725,6 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
					0x02, 0x00);
		snd_soc_component_update_bits(component, rx_path_cfg0_reg,
					0x02, 0x02);
		snd_soc_component_update_bits(component, rx_path_cfg3_reg,
					0x03, val);
	}

	if (SND_SOC_DAPM_EVENT_OFF(event)) {
@@ -1732,8 +1736,6 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
					0x01, 0x00);
		snd_soc_component_update_bits(component, comp_ctl0_reg,
					0x04, 0x00);
		snd_soc_component_update_bits(component, rx_path_cfg3_reg,
					0x03, 0x03);
	}

	return 0;