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Commit 102bdec1 authored by Jordan Crouse's avatar Jordan Crouse Committed by Greg Kroah-Hartman
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drm/msm/a5xx: Always set an OPP supported hardware value 



[ Upstream commit 0478b4fc5f37f4d494245fe7bcce3f531cf380e9 ]

If the opp table specifies opp-supported-hw as a property but the driver
has not set a supported hardware value the OPP subsystem will reject
all the table entries.

Set a "default" value that will match the default table entries but not
conflict with any possible real bin values. Also fix a small memory leak
and free the buffer allocated by nvmem_cell_read().

Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 45e61801

drivers/gpu/drm/msm/adreno/a5xx_gpu.c

+20 −7
Original line number Diff line number Diff line
@@ -1474,18 +1474,31 @@ static const struct adreno_gpu_funcs funcs = { 
static void check_speed_bin(struct device *dev)

{

	struct nvmem_cell *cell;

	u32 bin, val;

	u32 val;



	/*

	 * If the OPP table specifies a opp-supported-hw property then we have

	 * to set something with dev_pm_opp_set_supported_hw() or the table

	 * doesn't get populated so pick an arbitrary value that should

	 * ensure the default frequencies are selected but not conflict with any

	 * actual bins

	 */

	val = 0x80;



	cell = nvmem_cell_get(dev, "speed_bin");



	/* If a nvmem cell isn't defined, nothing to do */

	if (IS_ERR(cell))

		return;

	if (!IS_ERR(cell)) {

		void *buf = nvmem_cell_read(cell, NULL);



	bin = *((u32 *) nvmem_cell_read(cell, NULL));

	nvmem_cell_put(cell);

		if (!IS_ERR(buf)) {

			u8 bin = *((u8 *) buf);



			val = (1 << bin);

			kfree(buf);

		}



		nvmem_cell_put(cell);

	}



	dev_pm_opp_set_supported_hw(dev, &val, 1);

}