Commit 10286392 authored Nov 06, 2020 by Terry Zhou Committed by Greg Kroah-Hartman Dec 30, 2020

clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9



commit 6f37689cf6b38fff96de52e7f0d3e78f22803ba0 upstream.

There is an error in the current code that the XTAL MODE
pin was set to NB MPP1_31 which should be NB MPP1_9.
The latch register of NB MPP1_9 has different offset of 0x8.

Signed-off-by: Terry Zhou <bjzhou@marvell.com>
[pali: Fix pin name in commit message]
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 7ea82504 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20201106100039.11385-1-pali@kernel.org


Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

parent 7790c43a

drivers/clk/mvebu/armada-37xx-xtal.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -15,8 +15,8 @@
		#include <linux/platform_device.h>
		#include <linux/regmap.h>

		#define NB_GPIO1_LATCH 0xC
		#define XTAL_MODE BIT(31)
		#define NB_GPIO1_LATCH 0x8
		#define XTAL_MODE BIT(9)

		static int armada_3700_xtal_clock_probe(struct platform_device *pdev)
		{