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Commit 0f89b39b authored by Antoine Tenart's avatar Antoine Tenart Committed by Herbert Xu
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Documentation/bindings: Document the SafeXel cryptographic engine driver 



The Inside Secure Safexcel cryptographic engine is found on some Marvell
SoCs (7k/8k). Document the bindings used by its driver.

Signed-off-by: default avatarAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 52a33d99

Documentation/devicetree/bindings/crypto/inside-secure-safexcel.txt

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+29 −0
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Inside Secure SafeXcel cryptographic engine



Required properties:

- compatible: Should be "inside-secure,safexcel-eip197".

- reg: Base physical address of the engine and length of memory mapped region.

- interrupts: Interrupt numbers for the rings and engine.

- interrupt-names: Should be "ring0", "ring1", "ring2", "ring3", "eip", "mem".



Optional properties:

- clocks: Reference to the crypto engine clock.

- dma-mask: The address mask limitation. Defaults to 64.



Example:



	crypto: crypto@800000 {

		compatible = "inside-secure,safexcel-eip197";

		reg = <0x800000 0x200000>;

		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "mem", "ring0", "ring1", "ring2", "ring3",

				  "eip";

		clocks = <&cpm_syscon0 1 26>;

		dma-mask = <0xff 0xffffffff>;

		status = "disabled";

	};