Merge "ARM: dts: msm: Add jtagv8 devices for bengal"

		interrupts = <1 9 4>;

	};

	jtag_mm0: jtagmm@9040000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9040000 0x1000>;

		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU0>;

	};

	jtag_mm1: jtagmm@9140000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9140000 0x1000>;

		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU1>;

	};

	jtag_mm2: jtagmm@9240000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9240000 0x1000>;

		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU2>;

	};

	jtag_mm3: jtagmm@9340000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9340000 0x1000>;

		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU3>;

	};

	jtag_mm4: jtagmm@9440000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9440000 0x1000>;

		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU4>;

	};

	jtag_mm5: jtagmm@9540000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9540000 0x1000>;

		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU5>;

	};

	jtag_mm6: jtagmm@9640000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9640000 0x1000>;

		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU6>;

	};

	jtag_mm7: jtagmm@9740000 {

		compatible = "qcom,jtagv8-mm";

		reg = <0x9740000 0x1000>;

		reg-names = "etm-base";

		clocks = <&rpmcc RPM_SMD_QDSS_CLK>;

		clock-names = "core_clk";

		qcom,coresight-jtagmm-cpu = <&CPU7>;

	};

	timer {

		compatible = "arm,armv8-timer";

		interrupts = <1 1 0xf08>,