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Commit 0ee958e1 authored by Paul Burton's avatar Paul Burton Committed by Ralf Baechle
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MIPS: Coherent Processing System SMP implementation 



This patch introduces a new SMP implementation for systems implementing
the MIPS Coherent Processing System architecture. The kernel will make
use of the Coherence Manager, Cluster Power Controller & Global
Interrupt Controller in order to detect, bring up & make use of other
cores in the system. SMTC is not supported, so only a single TC per VPE
in the system is used. That is, this option enables an SMVP style setup
but across multiple cores.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6362/
Patchwork: https://patchwork.linux-mips.org/patch/6611/
Patchwork: https://patchwork.linux-mips.org/patch/6651/
Patchwork: https://patchwork.linux-mips.org/patch/6652/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent b86c2247

arch/mips/Kconfig

+21 −0
Original line number Diff line number Diff line
@@ -1887,6 +1887,7 @@ config MIPS_MT_SMTC 
	bool "Use all TCs on all VPEs for SMP (DEPRECATED)"

	depends on CPU_MIPS32_R2

	depends on SYS_SUPPORTS_MULTITHREADING

	depends on !MIPS_CPS

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select MIPS_MT
@@ -2003,6 +2004,23 @@ config MIPS_CMP 
	help

	  Enable Coherency Manager processor (CMP) support.



config MIPS_CPS

	bool "MIPS Coherent Processing System support"

	depends on SYS_SUPPORTS_MIPS_CPS

	select MIPS_CM

	select MIPS_CPC

	select MIPS_GIC_IPI

	select SMP

	select SYNC_R4K if (CEVT_R4K || CSRC_R4K)

	select SYS_SUPPORTS_SMP

	select WEAK_ORDERING

	help

	  Select this if you wish to run an SMP kernel across multiple cores

	  within a MIPS Coherent Processing System. When this option is

	  enabled the kernel will probe for other cores and boot them with

	  no external assistance. It is safe to enable this when hardware

	  support is unavailable.



config MIPS_GIC_IPI

	bool
@@ -2191,6 +2209,9 @@ config SMP_UP 
config SYS_SUPPORTS_MIPS_CMP

	bool



config SYS_SUPPORTS_MIPS_CPS

	bool



config SYS_SUPPORTS_SMP

	bool

arch/mips/include/asm/smp-cps.h

0 → 100644
+33 −0
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2013 Imagination Technologies

 * Author: Paul Burton <paul.burton@imgtec.com>

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */



#ifndef __MIPS_ASM_SMP_CPS_H__

#define __MIPS_ASM_SMP_CPS_H__



#ifndef __ASSEMBLY__



struct boot_config {

	unsigned int core;

	unsigned int vpe;

	unsigned long pc;

	unsigned long sp;

	unsigned long gp;

};



extern struct boot_config mips_cps_bootcfg;



extern void mips_cps_core_entry(void);



#else /* __ASSEMBLY__ */



.extern mips_cps_bootcfg;



#endif /* __ASSEMBLY__ */

#endif /* __MIPS_ASM_SMP_CPS_H__ */

arch/mips/include/asm/smp-ops.h

+9 −0
Original line number Diff line number Diff line
@@ -100,4 +100,13 @@ static inline int register_vsmp_smp_ops(void) 
#endif

}



#ifdef CONFIG_MIPS_CPS

extern int register_cps_smp_ops(void);

#else

static inline int register_cps_smp_ops(void)

{

	return -ENODEV;

}

#endif



#endif /* __ASM_SMP_OPS_H */

arch/mips/kernel/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o 
obj-$(CONFIG_MIPS_MT_SMTC)	+= smtc.o smtc-asm.o smtc-proc.o

obj-$(CONFIG_MIPS_MT_SMP)	+= smp-mt.o

obj-$(CONFIG_MIPS_CMP)		+= smp-cmp.o

obj-$(CONFIG_MIPS_CPS)		+= smp-cps.o cps-vec.o

obj-$(CONFIG_MIPS_GIC_IPI)	+= smp-gic.o

obj-$(CONFIG_CPU_MIPSR2)	+= spram.o

arch/mips/kernel/asm-offsets.c

+13 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <linux/suspend.h>

#include <asm/ptrace.h>

#include <asm/processor.h>

#include <asm/smp-cps.h>



#include <linux/kvm_host.h>
@@ -397,3 +398,15 @@ void output_kvm_defines(void) 
	OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);

	BLANK();

}



#ifdef CONFIG_MIPS_CPS

void output_cps_defines(void)

{

	COMMENT(" MIPS CPS offsets. ");

	OFFSET(BOOTCFG_CORE, boot_config, core);

	OFFSET(BOOTCFG_VPE, boot_config, vpe);

	OFFSET(BOOTCFG_PC, boot_config, pc);

	OFFSET(BOOTCFG_SP, boot_config, sp);

	OFFSET(BOOTCFG_GP, boot_config, gp);

}

#endif