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Commit 0ecf7170 authored by Asha Magadi Venkateshamurthy's avatar Asha Magadi Venkateshamurthy
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thermal: adc_tm: adc_init for sdm660 



Added initialization for PMIC4 to support SDM660.

Change-Id: I9703bb8dee21ee084917b044f7aa83a5087b49b4
Signed-off-by: default avatarAsha Magadi Venkateshamurthy <amagad@codeaurora.org>
parent 9f6b4236

drivers/thermal/qcom/adc-tm5.c

+31 −11
Original line number Diff line number Diff line
@@ -28,6 +28,9 @@ 
#define ADC_TM_MEAS_INTERVAL_CTL		0x44

#define ADC_TM_MEAS_INTERVAL_CTL2		0x45



#define ADC_TM_MEAS_INTERVAL_CTL_660		0x50

#define ADC_TM_MEAS_INTERVAL_CTL2_660		0x51



#define ADC_TM_MEAS_INTERVAL_CTL2_SHIFT		0x4

#define ADC_TM_MEAS_INTERVAL_CTL2_MASK		0xf0

#define ADC_TM_MEAS_INTERVAL_CTL3_MASK		0xf
@@ -1035,22 +1038,31 @@ static int adc_tm5_init(struct adc_tm_chip *chip, uint32_t dt_chans) 
{

	u8 buf[4], channels_available, meas_int_timer_2_3 = 0;

	int ret;

	int dig_param_len = 4;

	bool pmic_subtype_660 = false;

	unsigned int offset_btm_idx = 0, i;



	ret = adc_tm5_read_reg(chip, ADC_TM_NUM_BTM, &channels_available, 1);

	if ((chip->pmic_rev_id) &&

		(chip->pmic_rev_id->pmic_subtype == PM660_SUBTYPE)) {

		dig_param_len = 2;

		pmic_subtype_660 = true;

	} else {

		ret = adc_tm5_read_reg(chip, ADC_TM_NUM_BTM,

					&channels_available, 1);

		if (ret < 0) {

			pr_err("read failed for BTM channels\n");

			return ret;

		}



		if (dt_chans > channels_available) {

		pr_err("Number of nodes greater than channels supported:%d\n",

			pr_err("More nodes than channels supported:%d\n",

						channels_available);

			return -EINVAL;

		}

	}



	ret = adc_tm5_read_reg(chip,

			ADC_TM_ADC_DIG_PARAM, buf, 4);

			ADC_TM_ADC_DIG_PARAM, buf, dig_param_len);

	if (ret < 0) {

		pr_err("adc-tm block read failed with %d\n", ret);

		return ret;
@@ -1072,10 +1084,18 @@ static int adc_tm5_init(struct adc_tm_chip *chip, uint32_t dt_chans) 
	buf[3] = meas_int_timer_2_3;



	ret = adc_tm5_write_reg(chip,

			ADC_TM_ADC_DIG_PARAM, buf, 4);

			ADC_TM_ADC_DIG_PARAM, buf, dig_param_len);

	if (ret < 0)

		pr_err("adc-tm block write failed with %d\n", ret);



	if (pmic_subtype_660) {

		ret = adc_tm5_write_reg(chip,

				ADC_TM_MEAS_INTERVAL_CTL_660, &buf[2], 2);



		if (ret < 0)

			pr_err("adc-tm block write failed with %d\n", ret);

	}



	spin_lock_init(&chip->adc_tm_lock);

	mutex_init(&chip->adc_mutex_lock);