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Commit 0ea04c73 authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Marc Zyngier
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dt-bindings: Add description of Socionext EXIU interrupt controller



Add a description of the External Interrupt Unit (EXIU) interrupt
controller as found on the Socionext SynQuacer SoC.

Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent 6ef930f2
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Socionext SynQuacer External Interrupt Unit (EXIU)

The Socionext Synquacer SoC has an external interrupt unit (EXIU)
that forwards a block of 32 configurable input lines to 32 adjacent
level-high type GICv3 SPIs.

Required properties:

- compatible           : Should be "socionext,synquacer-exiu".
- reg                  : Specifies base physical address and size of the
                         control registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells     : Specifies the number of cells needed to encode an
                         interrupt source. The value must be 3.
- interrupt-parent     : phandle of the GIC these interrupts are routed to.
- socionext,spi-base   : The SPI number of the first SPI of the 32 adjacent
                         ones the EXIU forwards its interrups to.

Notes:

- Only SPIs can use the EXIU as an interrupt parent.

Example:

	exiu: interrupt-controller@510c0000 {
		compatible = "socionext,synquacer-exiu";
		reg = <0x0 0x510c0000 0x0 0x20>;
		interrupt-controller;
		interrupt-parent = <&gic>;
		#interrupt-cells = <3>;
		socionext,spi-base = <112>;
	};